{"id":14,"date":"2017-07-07T20:21:07","date_gmt":"2017-07-07T20:21:07","guid":{"rendered":"http:\/\/utsaengineer.wpengine.com\/faculty-page-example\/?page_id=14"},"modified":"2026-04-16T19:19:44","modified_gmt":"2026-04-17T00:19:44","slug":"publications","status":"publish","type":"page","link":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"<h4><span style=\"font-family: helvetica, arial, sans-serif;font-size: 14pt;color: #0000ff\"><u>Granted<\/u><u> Patents:<\/u><\/span><\/h4>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 12,261,937<\/strong>, Mar 2025: &#8220;Method &amp; Apparatus for an Ultra Low Power VLSI Implementation of the 128-Bit AES Algorithm Using a Novel Approach to the Shiftrow Transformation&#8221;, (Additional claims on Patent # 11,948,596) A. Muthineni and E. John<\/span><\/li>\n<\/ul>\n<ul style=\"list-style-type: disc\">\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 12,094,243, <\/strong>Sep 2024, <\/span>&#8220;Method and Apparatus for Discreet Facial Recognition on Pocket-Size Offline Mobile Platform with Augmented Reality Feedback with Real-Time Training Capability for Usage by Universal Users&#8221;, P. Stockton and E. John.<\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 11,948,596, <\/strong>April 2024, &#8220;<\/span>Method and Apparatus for Defending Against Laser or Other Electromagnetic Wave-Based Audio Injection Attacks on Voice-Controllable Devices and Systems&#8221;. E. John and R. Krishnan.<\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 11,838,403<\/strong>, Dec 2023: &#8220;Method &amp; Apparatus for an Ultra Low Power VLSI Implementation of the 128-Bit AES Algorithm Using a Novel Approach to the Shiftrow Transformation&#8221;,\u00a0 A. Muthineni and E. John.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 10,891,110, <\/strong>Jan, 2021: <\/span>&#8220;AES\/CRC Engine Based on Resource Shared Galois Field Computation&#8221;\u00a0<span style=\"font-family: helvetica, arial, sans-serif\">S. Mostafa and E. John.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 10,359,832, <\/strong>July, 2019: &#8220;Method and Apparatus for Reducing Power and Cycle Requirement for FFT of ECG signals&#8221;, E. John and S. Mostafa<\/span><\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 8,250,350<\/strong>, August 21, 2012: \u201cComputer systems with non-volatile write-protected memory based operating systems and secure architecture\u201d, E.\u00a0John, Thomas John and Lizy John.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent # 8,214,629<\/strong>, July 3, 2012: \u201cComputer systems with secure instantly available applications using non-volatile write protected memory\u201d, E.\u00a0 John, Thomas John and Lizy John.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span style=\"font-family: helvetica, arial, sans-serif\"><strong>US Patent #<\/strong> <strong>6,824,480, <\/strong>November 30, 2004: \u201cMethod and apparatus for location of objects, and application to real time display of the position of players, equipment and officials during a sporting event\u201d, E.\u00a0John and H. Foltz.<\/span><\/li>\n<\/ul>\n<h2><span style=\"font-size: 14pt;font-family: helvetica, arial, sans-serif;color: #0000ff\"><strong><u>Pending Patent Applications<\/u><\/strong><\/span><\/h2>\n<ul style=\"list-style-type: disc\">\n<li>\u201cSystem and Method for Time Series Pattern Matching for Energy Efficient Applications\u201d, P. Sengupta and E. John, Application submitted to USPTO on August 2024.<\/li>\n<\/ul>\n<ul style=\"list-style-type: disc\">\n<li>&#8220;Semi-Streaming Data Flow Architecture with Layer-Type Specialized Processing Engines for the Implementation of Convolutional Neural Networks in Hardware.&#8221;, N. Shayduk and E. John; Application filed on April, 2022<\/li>\n<\/ul>\n<h2><span style=\"font-family: helvetica, arial, sans-serif;font-size: 14pt;color: #0000ff\"><strong>Book(s):<\/strong><\/span><\/h2>\n<ul>\n<li><span id=\"productTitle\" class=\"a-size-extra-large\">&#8220;Fundamentals of Logic Design&#8221;, Enhanced <\/span><span id=\"productSubtitle\" class=\"a-size-large a-color-secondary\">7th Edition, <\/span><span style=\"font-size: 1rem\">by Charles H. Roth, Jr.,\u00a0 Larry L. Kinney, and <strong>Eugene B. John<\/strong>, CENGAGE Learning, Boston, MA.\u00a0 (1\/1\/2020).<\/span><\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong> and J. Rubio, \u201cUnique Chips and Systems\u201d edited book; CRC Press, November 2007\n<div class=\"a-section a-spacing-none\">\n<p id=\"title\" class=\"a-spacing-none a-text-normal\">\n<\/div>\n<\/li>\n<\/ul>\n<h2><span style=\"font-family: helvetica, arial, sans-serif;font-size: 14pt;color: #0000ff\"><strong>Book Chapters: <\/strong><\/span><\/h2>\n<ul>\n<li>C. Davis, P. Stockton, Z. Susskind, <strong>E. John<\/strong> and L. K. John, &#8220;Characterization of Neuro-Symbolic AI and Graph Convolutional Network Workloads&#8221;, in <span class=\"x_ContentPasted0\"><em>Artificial Intelligence: Machine Learning, Convolutional Neural Networks and Large Language Models<\/em>, Editors: L. Deligiannidis, G. Dimitoglou, H. R. Arabnia, and A. P. Tafti, Publisher: De Gruyter, Berlin, Germany; July, 2024.<\/span><\/li>\n<\/ul>\n<ul style=\"list-style-type: disc\">\n<li><strong>E. John<\/strong>, \u201cSemiconductor Memory Circuits\u201d, in the <em>Computer Engineering Hand Book<\/em>, 2<sup>nd<\/sup> ed. Editor: V. Oklobdzija, CRC Press, pp. 5-1 to 5-27, 2008.<\/li>\n<\/ul>\n<ul style=\"list-style-type: disc\">\n<li><strong>E. John<\/strong>, \u201cVLSI Circuits\u201d, in the <em>Computer Engineering Hand Book<\/em>, Editor: V. Oklobdzija, CRC Press, pp. 2.1 \u2013 2.20, 2002<\/li>\n<\/ul>\n<ul style=\"list-style-type: disc\">\n<li>L. John and <strong>E. John<\/strong>, \u201cBit-Slice Computers\u201d, in the<em> Encyclopedia of Electrical and Electronics Engineering<\/em>, Supplement 1, Editor: J.G.Webster, John Wiley and Sons, Inc. pp. 39-44, 1999.<\/li>\n<\/ul>\n<h2><span style=\"font-family: helvetica, arial, sans-serif;font-size: 14pt;color: #0000ff\"><strong>Journal and Conference Publications:<\/strong><\/span><\/h2>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">C. Davis, P. Stockton, E. Shojae, J. Ryoo and <strong>E. John <\/strong>&#8221; Hardware Acceleration for Graph Neural Networks&#8221; accepted for publications in the <\/span>23rd ACM International Conference on Computing Frontiers (CF&#8217;26) May 19-21, 2026, Catania, Sicily, Italy (Poster Session).<\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">S. Aphale and <strong>E<\/strong>.<strong> John<\/strong>, &#8220;Integrating Vision Transformers and Generative Models for High Accuracy Breast Cancer Detection from Histopathology Images&#8221; in the 5th IEEE International Conference on Computing and Machine Intelligence (ICMI-2026), April 9 &#8211; 10, Al Ahsa, Saudi Arabia.<\/span><\/li>\n<\/ul>\n<ul>\n<li>K. Baby, L. K. John, P. Lima, F. Franca and <strong>E. John<\/strong>, &#8220;<span data-olk-copy-source=\"MessageBody\">CA-WNN: Improving Weightless Neural Networks using Cellular Automata Feature Extraction&#8221;, in the 5th IEEE International Conference on Computing and Machine Intelligence (ICMI-2026), April 9 &#8211; 10, Al Ahsa, Saudi Arabia.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">A. Jha, S. Nag, I. D. S. Miranda, F. M. G. Franca, L. John, P. M. V. Lima and <strong>E. John<\/strong>, \u201cArrhythmia Classification at the Edge Using a Weightless Neural Network Hardware Accelerator\u201d, <span class=\"C9DxTc \">The 2<\/span><span class=\"C9DxTc \">2nd<\/span><span class=\"C9DxTc \"> International Symposium on Applied Reconfigurable Computing (ARC-2026), <\/span><span style=\"font-size: 1rem\">\u00a0<\/span><span style=\"font-size: 1rem\">April 8-10, 2026, Cagliari, Italy.<\/span><\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">T. Kholay, A. Kedilaya, A. Arora, <strong>E. John<\/strong>, J. Kulkarni and L. John &#8220;\u201cLearning Based Presilicon Estimation of Design Area from Early EDA Metrics&#8221;, <\/span>The 2<span class=\"C9DxTc \" style=\"font-size: 1rem\">2nd<\/span><span class=\"C9DxTc \" style=\"font-size: 1rem\"><span class=\"C9DxTc \"> International Symposium on Applied Reconfigurable Computing (ARC-2026), <\/span><\/span><span style=\"font-size: 1rem\">\u00a0<\/span><span style=\"font-size: 1rem\">April 8-10, 2026, Cagliari, Italy.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\"><strong>E. John <\/strong>and L. John, &#8220;Artificial Intelligence and Smart Sensors Usher a New Era in Patient Care&#8221;, IEEE Computer Magazine, pp 85-94, January 2026.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">I. D. S. Miranda, V. Pillai, T. Musale, M. Jadhao, P. C. R. S. Neto, Z. Susskind, A. Bacellar, M. Lhostis, P.\u00a0 M. V. Lima, D. L. C. Dutra, <strong>E. John<\/strong>, M. Breternitz Jr., F. M. G. Franc\u00b8a , E. Ozer, and L. K. John,\u00a0 &#8220;Weightless Neural Networks on Flexible Substrates: A Novel Approach to Wearable Machine Learning&#8221;,\u00a0 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp 444 &#8211; 452,\u00a0<\/span>\n<div class=\"u-pb-1 stats-document-abstract-publishedIn\" data-analytics_identifier=\"document_abstract_published_in\" data-analytics_payload=\"{&quot;docType&quot;: &quot;Journal&quot;}\" data-tealium_data=\"{&quot;docType&quot;: &quot;Journal&quot;}\">Volume: 34, Issue 2, February 2026.<\/div>\n<\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">S. Aphale, A. Kalapa, E. Tolliver, and <strong>E. John<\/strong>, &#8220;Synthetic Medical Image Generation with Conditional Generative Adversarial Networks for Enhanced Diagnostic Performance&#8221;, in The\u00a0 12th Annual International Conference on Computational Science and Computational Intelligence (CSCI-25), December 3-5, 2025 &#8211; Las Vegas, USA.<\/span><\/li>\n<\/ul>\n<ul>\n<li>E. Shojae, W. Dai, A. Jha, <strong>E. John<\/strong> and J. Ryoo, &#8220;Hardware-Based Reinforcement Learning for Adaptive Dynamic Voltage and Frequency Scaling&#8221;, 8th IBM\/IEEE AI Compute Symposium, November 13,\u00a0 2025 (Poster Session).<\/li>\n<\/ul>\n<ul>\n<li>P. Stockton, C. Davis, J. Ryoo and <strong>E. John<\/strong>, &#8220;<span data-olk-copy-source=\"MessageBody\">Accelerating Neuro-Symbolic AI with CUTLASS-Optimized CUDA Kernels&#8221;, 8th IBM\/IEEE AI Compute Symposium, November 13,\u00a0 2025 (Poster Session).<\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\"><span data-olk-copy-source=\"MessageBody\">S. Nag, A. Bacellar, Z. Susskind, A. Jha, L. Liberty, A. Sivakumar, <strong>E. John<\/strong>, K. Kailas, P. Lima, N. Yadwadkar, F. Fran\u00e7a, L. K. John, &#8220;LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons&#8221;, the <\/span><\/span>International Conference on Field Programmable Technology <span data-olk-copy-source=\"MessageBody\">(FPT 2025), <\/span>2-5th December 2025, Shanghai, China<\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\"><span data-olk-copy-source=\"MessageBody\">L. John, P. Lima, A. Bacellar, S. Nag, <strong>E. John<\/strong> and F. Fran\u00e7a &#8220;LUT Based Neural Networks as Neuro-Symbolic Systems&#8221;, <\/span><\/span><em>19th International Conference on Neurosymbolic Learning and Reasoning (NeSy 2025)<\/em>, Sep 2025, Santa Cruz, CA.<\/li>\n<\/ul>\n<ul>\n<li>G. Jha, A. Jha and <strong>E. John<\/strong>, &#8220;An EEG Based High Accuracy CNN for Emotional Health Detection&#8221;, the <span data-olk-copy-source=\"MessageBody\"><em>27th International Conference on Artificial Intelligence (ICAI-25)<\/em>, July 21 &#8211; 24, 2025, Las Vegas, NV.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">J. Hollen and <strong>E. John<\/strong>, &#8220;Mars Surface Novelty Detection Using Binarized Neural Networks&#8221;, <em>MWSCAS 2025, <\/em><\/span><em>IEEE International Midwest Symposium on Circuits and Systems<\/em>,\u00a0 August 10-13, 2025, Lansing, MI.<\/li>\n<\/ul>\n<ul style=\"list-style-type: disc\">\n<li>C. Davis, P. Stockton, J. Ryoo and <strong>E. John<\/strong>, &#8220;Improving Energy Efficiency of Graph Neural Network Execution by using PIM Architecture&#8221;,\u00a0 <em>1st International Workshop on Data Center Energy Efficiency (DCEE-2025)<\/em> @ISCA 2025, June 21, 2025, Tokyo, Japan.<\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">S. Aphale and <strong>E. John<\/strong>, &#8220;Cross Framework Comparative Analysis of Deep-ArrhyNet for High-Accuracy Arrhythmia Classification&#8221;, the <em>17th International Conference on Smart Computing and Artificial Intelligence (SCAI 2025),<\/em> July 13-19, Kitakyushi, Japan.<\/span><\/li>\n<\/ul>\n<ul>\n<li><span data-olk-copy-source=\"MessageBody\">V. Pillai, S. Nag, M. Jadhao, A. Bacellar, I. Miranda, F. Franca, P. Lima, D. Dutra, L. John and <strong>E. John<\/strong>, &#8220;Edge-Optimized Weightless Neural Network for Low-Power Wearable Arrhythmia Detection&#8221;, <em>IEEE 18th Dallas Circuits and Systems Conference (DCAS)<\/em>, Dallas, TX, April, 2025.<\/span><\/li>\n<\/ul>\n<ul>\n<li>C. Davis, P. Stockton, M. Zhang, J. Ryoo and <strong>E. John<\/strong>, &#8220;Microarchitectural Characterization of LightGCN and ExpressGNN and Architectural Implications&#8221;, (Poster Presentation) <em>HiPEAC 2025: The 20th International Conference on High Performance, Edge and Cloud Computing<\/em>, Jan 20 &#8211; 22, 2025, Barcelona, Spain.<\/li>\n<\/ul>\n<ul>\n<li>G. Jha, A. Jha and <strong>E. John<\/strong>, &#8221; Performance Comparison of High Accuracy CNNs for Brain Tumor Detection Using Transfer Learning&#8221;\u00a0\u00a0<em>t<\/em><em>he 2024 International Conference on Computational Science and Computational Intelligence (CSCI&#8217;24)<\/em>: December 11-13, 2024; Las Vegas.<\/li>\n<\/ul>\n<ul>\n<li>V. Pillai, I. Miranda, T Musale, M. Jadhao, P. Neto, Z. Susskind, A. Bacellar, M. Lhostis, P. Lima, D. Dutra, <strong>E. John<\/strong>, M. Breternitz Jr., F. Franca, E. Ozer and L. K. John, \u201carrWNN: Arrhythmia-detecting Weightless Neural Network FlexIC\u201d, in the Proceeding of the <em>IEEE <\/em><em style=\"font-size: 1rem\">International Flexible Electronics Technology Conference (IFETC-2024)<\/em><span style=\"font-size: 1rem\">, Bologna, Italy, <\/span>15-18 September 2024.<\/li>\n<\/ul>\n<ul>\n<li>S. Nag, Z. Susskind, A. Arora, A. Bacellar, D. Dutra, I Miranda, K. Kailas, <strong>E. John<\/strong>, M Breternitz Jr., P. Lima, F. Franca, L. K. John, &#8220;LogicNets vs. ULEEN : Comparing two novel high throughput edge ML inference techniques on FPGA&#8221;, in the Proceeding of the<em> 67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2024)<\/em>, Springfield, MA, August 11 \u2013 14,\u00a0 2024.<\/li>\n<\/ul>\n<ul>\n<li>G. Jha, A Jha and <strong>E. John<\/strong>,\u00a0 &#8220;A High Accuracy CNN for Breast Cancer Detection using Mammography Images&#8221;,\u00a0<em style=\"font-size: 1rem\">67th <\/em><span style=\"font-size: inherit\"><em>\u00a0IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2024), Springfield, MA<\/em>, August 11 &#8211; 14, <\/span><span style=\"font-size: 1rem\">\u00a02024.<\/span><\/li>\n<\/ul>\n<ul>\n<li>A. Bacellar, Z. Susskind, M. Breternitz Jr, <strong>E. John, <\/strong>L. K. John, P. Lima and F. Franca, &#8220;Differentiable Weightless Neural Networks&#8221;, in the proceedings of the\u00a0 <em>41st International Conference on Machine Learning (ICML-2024)<\/em>, Vienna, Austria, July 21-27, 2024.<\/li>\n<\/ul>\n<ul>\n<li>P. Sengupta and <strong>E. John<\/strong> &#8220;Time Series Pattern Matching Technique for Low-Energy Arrhythmia Classification in Implantable Cardiac Devices&#8221; in the proceedings of the <em>3rd IEEE International Conference on Computing and Machine Intelligence (ICMI-2024)<\/em>. Michigan, April 13-14, 2024.<\/li>\n<\/ul>\n<ul>\n<li>A. Owahid, and <strong>E. John, <\/strong>&#8220;Instruction Profiling Based Predictive Throttling for Power and Performance&#8221;, in\u00a0<em>IEEE Transactions on Computers<\/em>, vol. 72, no. 12, pp. 3532-3545, Dec. 2023.<\/li>\n<\/ul>\n<ul>\n<li>L. John, F. Franca, S. Mitra, Z. Susskind, P. Lima, I. Miranda, <strong>E. John<\/strong>, D. Dutra and M. Breternitz, &#8220;Dendrite-inspired Computing to improve Resilience of Neural Networks to Faults in Emerging Memory Technologies&#8221;, in the\u00a0<em>Proceedings of <\/em>the <em>8th IEEE International Conference on Rebooting Computing (ICRC 2023),<\/em> 5-6, December, 2023; San Diego, CA.<\/li>\n<\/ul>\n<ul>\n<li>P. Stockton, C. Davis and <strong>E. John<\/strong>, &#8220;Microarchitecture Characterization and Analysis of Emerging Neuro-Symbolic A.I. Workloads&#8221;, in the\u00a0<em>Proceedings of t<\/em><em>he 2023 International Conference on Computational Science and Computational Intelligence (CSCI&#8217;23)<\/em>: December 13-15, 2023; Las Vegas.<\/li>\n<\/ul>\n<ul>\n<li>C. Davis, P. Stockton and <strong style=\"font-size: 1rem\">E. John<\/strong><span style=\"font-size: 1rem\">, &#8220;Profiling Analysis for Enhancing the Performance of Graph Neural Networks&#8221;, in the <\/span><em style=\"font-size: 1rem\">Proceedings of the 22nd IEEE International Conference on Machine Learning and Applications<\/em><span style=\"font-size: 1rem\">, December 15-17, 2023, Jacksonville, Florida.<\/span><\/li>\n<\/ul>\n<ul>\n<li>P. Stockton, and <strong>E. John<\/strong>, \u201cNeuro-Symbolic Workload Micro-Architecture Analysis and Characterization of the Neural Logic Machine\u201d, SRC (Semiconductor Research Corporation) TECHCON 2023, Austin, Texas, September 10-12, 2023.<\/li>\n<\/ul>\n<ul>\n<li>Y. Oleyaeimotlagha, T. Banerjee, A. Taha and <strong>E. John<\/strong>, &#8220;Quickest Change Detection in Statistically Periodic Processes with Unknown Post-Change Distribution&#8221;, <em>Sequential Analysis: Design Methods and Applications, Pages 404-437, Dec 2023.<\/em><\/li>\n<\/ul>\n<ul>\n<li>C. Davis, P. Stockton, Z. Susskind, <strong>E. John<\/strong>, and Lizy K. John, &#8220;Characterization of Emerging AI Workloads: Neural Logic Machines and Graph Convolutional Networks&#8221; the <em>2022 International Conference on Computational Science and Computational Intelligence (CSCI&#8217;22),<\/em> December 14-16, 2022; Las Vegas.<\/li>\n<\/ul>\n<ul>\n<li>E. Tolliver, V. Pillai, A. Jha and <strong>E. John<\/strong>, &#8220;A Comparative Analysis of Half Precision Floating Point Representations in MACs for Deep Learning&#8221;, in the <em>Proc. of the International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME), <\/em><em>16-18 November 2022, Maldives<\/em><\/li>\n<\/ul>\n<ul>\n<li>S. Aphale, A. Jha, and <strong>E. John<\/strong>, &#8220;High Accuracy Arrhythmia Classification using Transfer Learning with Fine-Tuning&#8221;\u00a0 <em>2022 IEEE 13th Annual Ubiquitous Computing, Electronics &amp; Mobile Communication Conference (UEMCON),<\/em> Virtual Conference, New York, USA 26 &#8211; 29 October, 2022<\/li>\n<\/ul>\n<ul>\n<li>A. Jha, <strong>E. John<\/strong>, and T. Banerjee, &#8220;Multi-Class Classification of Dementia from MRI Images Using Transfer Learning<span style=\"font-size: 1rem\">&#8221;\u00a0 <em>2022 IEEE 13th Annual Ubiquitous Computing, Electronics &amp; Mobile Communication Conference (UEMCON),<\/em> Virtual Conference, New York, USA 26 &#8211; 29 October, 2022<\/span><\/li>\n<\/ul>\n<ul>\n<li>A. Jha, <strong>E. John<\/strong>\u00a0and T. Banerjee,&#8221; Transfer Learning for COVID-19 and Pneumonia Detection using Chest X-Rays&#8221;, <em>65th <\/em><span style=\"font-size: inherit\"><em>\u00a0IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022), <\/em>\u00a0 Fukuoka, Japan (Virtual Conference), August 7 &#8211; 10, <\/span>\u00a02022.<\/li>\n<\/ul>\n<ul>\n<li>C. Davis and <strong>E. John<\/strong>, &#8220;Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices&#8221;, <em style=\"font-size: 1rem\">65th <\/em><span style=\"font-size: inherit\"><em>\u00a0IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022), <\/em>\u00a0 Fukuoka, Japan (Virtual Conference), August 7 &#8211; 10, <\/span><span style=\"font-size: 1rem\">\u00a02022.<\/span><\/li>\n<\/ul>\n<ul>\n<li>W. Chen, T. Banerjee, <strong>E. John<\/strong>, &#8220;A Meta-Transfer Learning Approach to ECG Arrhythmia Detection&#8221;, the\u00a0 44th Annual International Conference of the IEEE Engineering in Medicine &amp; Biology Society (EMBC), Glasgow, United Kingdom 11-15 July 2022.<\/li>\n<\/ul>\n<ul>\n<li>S. D. Sakyi,\u00a0 V. Kothavade and <strong>E.\u00a0 John<\/strong>, &#8220;Breast Cancer Detection using Deep Learning&#8221;, <span style=\"font-size: 1rem\">Viva Science SA, San Antonio, <\/span><span style=\"font-size: 1rem\">April 9, 2022 (Poster Session).<\/span><\/li>\n<\/ul>\n<ul>\n<li>Z. Susskind, B. Arden, L. K. John, P. Stockton, and <strong>E. B. John<\/strong>, &#8220;Characterizing Neuro-Symbolic Workloads&#8221;, IBM IEEE CAS\/EDS AI Compute Symposium, October 13-14,\u00a0 2021 (Poster Session).<\/li>\n<\/ul>\n<ul>\n<li>S. Aphale, <strong>E. John<\/strong> and T. Banerjee, &#8220;ArrhyNet: A High Accuracy Arrhythmia Classification Convolutional Neural Network&#8221;, the 2021 IEEE 64th International Midwest Symposium on Circuits &amp; Systems (MWSCAS 2021), August 9-11, 2021<\/li>\n<\/ul>\n<ul>\n<li><span class=\"markhqb85rjm2\" data-markjs=\"true\" data-ogac=\"\" data-ogab=\"\" data-ogsc=\"\" data-ogsb=\"\">T. <\/span><span class=\"mark2gh31iwcg\" data-markjs=\"true\" data-ogac=\"\" data-ogab=\"\" data-ogsc=\"\" data-ogsb=\"\">Banerjee<\/span>, A. Taha and <strong>E. John<\/strong>, &#8220;Robust Quickest Change Detection in Statistically Periodic Processes&#8221;, the 2021 IEEE International Symposium on Information Theory (ISIT-2021), Melbourne, Victoria, Australia, 12-20 July, 2021<\/li>\n<\/ul>\n<ul>\n<li>Banerjee, S. Padhy, A. Taha and <strong>E. John<\/strong>, \u201cQuickest Joint Detection and Classification of Faults in Statistically Periodic Processes, In Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Toronto, Canada, June 2021<\/li>\n<\/ul>\n<ul>\n<li>N. Shaydyuk and <strong>E. John<\/strong>, &#8220;FPGA Implementation of MobileNetV2 CNN Model Using Semi-Streaming Architecture for Low Power Inference\u00a0 Applications&#8221;, 18th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA-2020), England, UK, 17-19, pp. 160-167, December 2020.<\/li>\n<\/ul>\n<ul>\n<li>K. Leochico and <strong>E. John, <\/strong>&#8220;Evaluating Cloud Auto-Scaler Resource Allocation Planning Under High-Performance Computing Workloads&#8221;, 19th International Conference on Ubiquitous Computing and Communications (IUCC-2020), UK,\u00a0 December 2020.<\/li>\n<\/ul>\n<ul>\n<li>S. Verma, Q. Wu, B. Hanindhito, G. Jha, <strong>E. John<\/strong>, R. Radhakrishnan and L. K. John, \u201cDemystifying the MLPerf Training Benchmark Suite\u201d, In the Proc. of the 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS&#8217;20), Boston, MA, August 2020.<\/li>\n<\/ul>\n<ul>\n<li>T. Banerjee, E. Adib, A. Taha and <strong>E. John<\/strong>, &#8220;Sequential methods for detecting a change in the distribution of an episodic process,&#8221; In the Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Virtual Barcelona, Spain, May 2020.<\/li>\n<\/ul>\n<ul>\n<li>T. K. Kodali, Y. Zhang, <strong>E. John<\/strong> and W. Lin, \u201cAn Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction\u201d, <em>Journal of Information Science and Engineering, pp 1-12<\/em>, Jan 2020.<\/li>\n<\/ul>\n<ul>\n<li>S. Mostafa and\u00a0 <strong>E. John, <\/strong>\u201cResource Shared Galois Field Computation for Energy Efficient AES\/CRC in IoT Applications\u201d, <em>IEEE Transactions on Sustainable Computing, pp. 340-348, vol. 4, Dec. 2019.<\/em><\/li>\n<\/ul>\n<ul>\n<li>A. Owahid, and <strong>E. John <\/strong>&#8220;Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction&#8221;, <em>31st International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2019<\/em>, October 15-18, 2019 &#8211; Campo Grande, MS, Brazil.<\/li>\n<\/ul>\n<ul>\n<li>S. Mostafa, <strong>E. John<\/strong> and M. Panday, \u201cDesign and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers\u201d, <em>IEEE Transactions on VLSI Systems, <\/em>Vol. 27. No. 4, pp. 983- 987, April, 2019.<\/li>\n<\/ul>\n<ul>\n<li>C. Davis, A. Muthineni, and <strong>E. John<\/strong>, &#8220;Low-Power Advanced Encryption Standard for Implantable Cardiac Devices&#8221;, <em>62<sup>nd<\/sup><\/em><span style=\"font-size: inherit\"><em> IEEE International Midwest Symposium on Circuits and Systems<\/em>,\u00a0 <\/span>Dallas, TX, Aug. 4-7, 2019.<\/li>\n<\/ul>\n<ul>\n<li>L. John, S. Verma, Q. Wu, B. Hanindhito, R. Radhakrishnan, G, Jha and <strong>E. John<\/strong>, &#8221; Demystifying Hardware Infrastructure Choices for Deep Learning using MLPref&#8221;, <em>NVIDIA GPU Technology Conference (GTC-2019)<\/em>, San Jose, CA, March 2019.<\/li>\n<\/ul>\n<ul>\n<li>S. Verma, Q. Wu, B. Hanindhito, G. Jha, <strong>E. John<\/strong>, R. Radhakrishnan, and L. K.\u00a0 John,&#8221;Metrics for Machine Learning Workload Benchmarking&#8221;, <em>International Workshop on Performance Analysis of Machine Learning Systems (FastPath) in conjunction with ISPASS 2019<\/em>. March 2019.<\/li>\n<\/ul>\n<ul>\n<li>J. Whitehouse, Q. Wu, S. Song, <strong>E. John<\/strong>, A. Gerstlauer, and L. K. John, \u201cA Study of Core Utilization and Residency in Heterogeneous Smartphone Architectures\u201d, <em>ACM International Conference on Performance Engineering (ICPE).<\/em> April 2019.<\/li>\n<\/ul>\n<ul>\n<li>A. Owahid, and <strong>E. John<\/strong>, \u201cWasted Dynamic Power and Correlation to Instruction Set Architecture for CPU Throttling\u201d <em>The Journal of Supercomputing<\/em>, pp. 2436-2454, Volume 75, Number 5, May 2019.<\/li>\n<\/ul>\n<ul>\n<li>E. Tolliver and <strong>E. John<\/strong>, \u201cPower Reduction in CNNs by Modifying Floating Point Number Format for Machine Learning\u201d <em>4th Annual Samsung Austin Research Center Technology Forum<\/em>, Austin, TX, Oct 16, 2018.<\/li>\n<\/ul>\n<ul>\n<li>G. Jha and <strong>E. John<\/strong>, \u201cPerformance Analysis of Single-Precision Floating-Point MAC for Deep Learning\u201d, <em>61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018),<\/em> Windsor, ON, Canada, August 5th-8th, 2018.<\/li>\n<\/ul>\n<ul>\n<li>T. A. Newton and <strong>E. John<\/strong>, \u201cA Metric for Measuring Power Efficiency and Data Throughput in Mobile <em>ad hoc<\/em> Networks\u201d, <em>International Journal of Parallel, Emergent and Distributed Systems,<\/em> pp. 556-571, March,\u00a0 2018.<\/li>\n<\/ul>\n<ul>\n<li>J. Portillo and\u00a0\u00a0<strong>E. John<\/strong>, &#8220;Using Static Hardware Wrappers to Thwart Hardware Trojans and Code Bugs at Runtime&#8221; <em>61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018)<\/em>, Windsor, ON, Canada, August 5th-8th, 2018.<\/li>\n<\/ul>\n<ul>\n<li>J. Portillo and\u00a0\u00a0<strong>E. John<\/strong>, &#8220;Detecting Vulnerabilities within Black Boxed CPUs using Assertion Based Verification for Enhanced Security&#8221;, <em>\u00a0The 2018 International Conference on Security and Management (SAM&#8217;18)<\/em>, Las Vegas, July 30 &#8211; August 2, 2018.<\/li>\n<\/ul>\n<ul>\n<li>S. Koppa and <strong>E. John<\/strong>, \u201cPerformance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices\u201d, <em>Journal of Low Power Electronics<\/em>, 14, 18 &#8211; 27., March, 2018.<\/li>\n<\/ul>\n<ul>\n<li>D. Vernor, S. Koppa, and <strong>E. John<\/strong>, \u201cStatic Noise Margin Optimized 11nm Shorted-Gate and Independent-Gate Low Power 6T FINFET SRAM Topologies\u201d, International<em> Journal of VLSI Design &amp; Communication Systems (VLSICS)<\/em>, 9(5)., October, 2018.<\/li>\n<\/ul>\n<ul>\n<li>H. Yan, L. Jiang, L. Duan, W. Lin and <strong>E. John<\/strong>, \u201cFlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance\u201d, <em>ACM Transactions on Embedded Computing Systems (TECS)<\/em>, Volume 16 Issue 5s, October 2017.<\/li>\n<\/ul>\n<ul>\n<li>A. Owahid and <strong>E. John<\/strong>, \u201cIdentifying Micro-ops for CPU Throttling to Reduce Wasted Dynamic Power\u201d <em>3<sup>rd<\/sup> Annual Samsung Austin Research Center Technology Forum<\/em>, Austin, TX, Oct 17, 2017.<\/li>\n<\/ul>\n<ul>\n<li>P. Mariano and <strong>E. John<\/strong>, &#8220;Reducing Branch Penalty by an Early Branch Resolution Technique&#8221;\u00a0 <em>4th Annual Samsung Austin Research Center Technology Forum<\/em>, Austin, TX, Oct 16, 2017.<\/li>\n<\/ul>\n<ul>\n<li>P. Sarva, S. Koppa, and <strong>E. John<\/strong>, \u201cAn Ultra-Low Power modified SERF Adder in Sub-threshold region for Bio-medical Applications\u201d, <em>The 3rd International Conference on Biomedical Engineering and Sciences, BIOENG&#8217;17<\/em>: Las Vegas, July 17-20, 2017.<\/li>\n<\/ul>\n<ul>\n<li>A. Owahid and <strong>E. John<\/strong>, \u201cRTL Level Instruction Profiling for CPU Throttling to Reduce Wasted Dynamic Power\u201d, <em>The 2017 International Symposium on Parallel And Distributed Computing And Computational Science<\/em>, Las Vegas, NV, 2017.<\/li>\n<\/ul>\n<ul>\n<li>J. Portillo and\u00a0\u00a0<strong>E. John<\/strong>, \u201cEnhancing Trojan Detection by Finding LTL and Taint Properties in RTL Circuit Designs: A Case Study\u201c, <em>The 2017 International Symposium on Cyber Warfare, Cyber Defense, and Cyber Security<\/em>, Las Vegas, NV, 14 \u2013 16, Dec 2017.<\/li>\n<\/ul>\n<ul>\n<li>J. Portillo, <strong>E. John<\/strong> and S. Narasimhan, \u201cBuilding Trust in 3PIP using Asset-based Security Property Verification\u201d <em>IEEE VLSI Test Symposium 2016<\/em>, Las Vegas, NV, April 25-27, 2016.<\/li>\n<\/ul>\n<ul>\n<li>S. Koppa, M. Mohandesi and <strong>E. John<\/strong> \u201cAn Ultra-Low Power CR-SAR A\/D Converter for Biomedical Applications\u201d, Journal of Low Power Electronics, Vol.12, No. 4., pp. 385\u2013393 (2016)<\/li>\n<\/ul>\n<ul>\n<li>S. Mostafa and <strong>E. John<\/strong>, \u201cReducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices\u201d, Journal of Low Power Electronics, Volume 12, Number 1, March 2016, pp. 21-29(9)<\/li>\n<\/ul>\n<ul>\n<li>S. Koppa, P. Syam, S. Nanduru and <strong>E. John<\/strong> \u201cA Quantitative Performance Analysis of FinFET Based Multiplier Circuits\u201d 59th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, UAE, 2016<\/li>\n<\/ul>\n<ul>\n<li>A. Ozer and <strong>E. John<\/strong>, \u201cImproving the Accuracy of Bluetooth Low Energy Indoor Positioning Using Kalman Filtering\u201d, The 2016 International Symposium on Internet of Things and Internet of Everything, , Las Vegas, Dec 15 \u2013 17, 2016<\/li>\n<\/ul>\n<ul>\n<li>S. Koppa, and <strong>E. John<\/strong> \u201cLeakage Current Compensation in Switched Capacitor Circuits for Implantable Cardiac Devices\u201d, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG&#8217;16), Las Vegas, NV, July 25 \u2013 28, 2016.<\/li>\n<\/ul>\n<ul>\n<li>S. Mostafa and <strong>E. John<\/strong> \u201cPerformance and Energy Evaluation of ARM Cortex Variants for Smart Cardiac Pacemaker Application\u201d, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG&#8217;16), Las Vegas, NV, July 25 \u2013 28, 2016.<\/li>\n<\/ul>\n<ul>\n<li>S. Erathne, P.S. Nair and <strong>E. John<\/strong>, \u201cA Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors\u201d, Journal of Low Power Electronics, Volume 11, Number 2, June 2015, pp. 103-111(9)<\/li>\n<\/ul>\n<ul>\n<li>Vasquez, C., Krishnan, R., and <strong>John, E<\/strong>. (2015). Time Series Forecasting of Cloud Data Center Workloads for Dynamic Resource Provisioning. Journal of Wireless Mobile Networks, Ubiquitous Computing and Dependable Applications, 6(3).<\/li>\n<\/ul>\n<ul>\n<li>Valliyappan, V., <strong>John, E<\/strong>., Krishnan, R., &amp; Nanduru, S. (2015). Design And Implementation of Low-Power Nanoscale Cryptosystem for Group-Centric Secure Information Sharing. Research Briefs on Information &amp; Communication Technology Evolution (Journal), 1(20).<\/li>\n<\/ul>\n<ul>\n<li>Ninglekhu, J., Krishnan, R., <strong>John, E<\/strong>., &amp; Panday, M. (2015). Securing Implantable Cardioverter Defibrillators Using Smartphones. Journal of Internet Services and Information Security, 5(2).<\/li>\n<\/ul>\n<ul>\n<li>M. Cheboli, P.S. Nair and <strong>E. John<\/strong>, Speed, Power and Area Performance of ALU Implementation in the Nanoscale Domain, International Journal of Engineering, Sciences and Management (IJESM), Vol 1, Issue 1, pp. 1 \u2013 9, Jan, 2015.<\/li>\n<\/ul>\n<ul>\n<li>S. Mostafa and <strong>E. John<\/strong> \u201cEvaluation of Embedded ISAs for Smart Cardiac Pacemaker Workloads\u201d, in the Proceedings of\u00a0 the 2015 International Conference on Biomedical Engineering and Sciences (BIOENG\u201915), Las Vegas, NV, July 27-30, 2015.<\/li>\n<\/ul>\n<ul>\n<li>C. Hurt and <strong>E. John<\/strong>, \u201cAnalysis of Memory Sensitive SPEC CPU2006 Integer Benchmarks for Big Data Benchmarking\u201d 1st Workshop on Performance Analysis of Big Data Systems (PABS &#8211; 2015), Austin, TX, Feb, 2015.<\/li>\n<\/ul>\n<ul>\n<li>N. Ferdous. B. Lee and <strong>E. John<\/strong>, \u201cPerformance Enhancement in Shared-Memory Multiprocessors Using Dynamically Classified Sharing Information\u201d 33rd IEEE &#8211; International Performance Computing and Communications Conference IPCCC 2014, Austin, TX, Dec 5 \u2013 7, 2014.<\/li>\n<\/ul>\n<ul>\n<li>N. Ferdous. B. Lee and <strong>E. John<\/strong> \u201cExploiting Reuse-Frequency with Speculative and Dynamic Updates in an Enhanced Directory Based Coherence Protocol\u201d, in The 2014 International Conference on Parallel and Distributed Processing Techniques and Applications PDPTA&#8217;14, pp. 334-350, Las Vegas, July 2014.<\/li>\n<\/ul>\n<ul>\n<li>C. Vazquez, R. Krishnan and <strong>E. John<\/strong>, \u201cCloud Computing Benchmarking: A Survey\u201d in the Proceedings of The 2014 International Conference on Grid &amp; Cloud Computing &amp; Applications GCA\u201914, pp. 15 \u2013 20, Las Vegas, July 2014<\/li>\n<\/ul>\n<ul>\n<li>Y. Zhang, M. Hays, W. Lin, and <strong>E. John<\/strong>, \u201cAutonomous Control of Issue Queue Utilization for Simultaneous Multi-Threading Processors, The 22nd High Performance Computing Symposium (HPC 2014), April 13-16, 2014, Tampa, FL.<\/li>\n<\/ul>\n<ul>\n<li>J. Whitehouse and <strong>E. John<\/strong>, \u201cLeakage and Delay Analysis in FinFET Array Multipliers\u201d, in 57th IEEE International Midwest Symposium on Circuits and Systems (MWCAS), Aug 3 \u2013 6, 2014.<\/li>\n<\/ul>\n<ul>\n<li>K. Leochico and <strong>E. John<\/strong>, \u201cData Retention Voltage Analysis of Various Low-Power SRAM topologies\u201d, in 57th IEEE International Midwest Symposium on Circuits and Systems (MWCAS), Aug 3 \u2013 6, 2014.<\/li>\n<\/ul>\n<ul>\n<li>F. Hurtado and <strong>E. John<\/strong>, \u201cA Comparative Analysis of Leakage Reduction Techniques in Nanoscale CMOS Arithmetic Circuits\u201d, in ASEE\/GSW Annual Conference, New Orleans, April 2 \u2013 4, 2014.<\/li>\n<\/ul>\n<ul>\n<li>H. Rios, J. Guo, B. Liu and <strong>E. John<\/strong>, \u201cLEON2 Timing Performance in Automotive, Office Automation and Security Applications\u201d, in ASEE\/GSW Annual Conference, New Orleans, April 2 \u2013 4, 2014.<\/li>\n<\/ul>\n<ul>\n<li>M. Talsania and <strong>E. John<\/strong>, \u201cA Comparative Analysis of Parallel Prefix Adders\u201d, Proceedings of the 2013 International Conference on Computer Design, pp. 29 \u2013 36, Las Vegas, July 2013.<\/li>\n<\/ul>\n<ul>\n<li>R. Krishnan and <strong>E. John<\/strong>, \u201cDesign of a Curriculum on Cloud Computing\u201d Proceedings of the 2013 International Conference on Frontiers in Education: Computer Science &amp; Computer Engineering\u201d, pp 312 \u2013 315, Las Vegas, 2013.<\/li>\n<\/ul>\n<ul>\n<li>P. Mishra , <strong>E. John<\/strong>, and W. Lin, \u201cStatic Noise Margin and Power Dissipation Analysis of various SRAM Topologies \u201d, IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) 2013Columbus Ohio, August 2013.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, S. Erathne and <strong>E. John<\/strong>, \u201cProbability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance\u201d, Journal of Low Power Electronics. Volume 8, Number 1, pp. 1-8, April 2012.<\/li>\n<\/ul>\n<ul>\n<li>M. Debnath, W. Lin and <strong>E. John<\/strong>, \u201cAdaptive Instruction Dispatching Techniques for Simultaneous Multi-Threading (SMT) Processors\u201d, Journal of Computers and Electrical Engineering, Aug. 2012<\/li>\n<\/ul>\n<ul>\n<li>D. Subedi and <strong>E. John<\/strong>, \u201cStand-by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits using Self Adjustable Voltage level Circuit\u201d, International Journal of VLSI Design &amp; Communication Systems, Vol. 3, No. 5, pp 1-12, October 2012.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, D. Kudithipudi, <strong>E. John<\/strong> and F. W. Hudson \u201cExecution Characteristics of Embedded Applications on Pentium-4 Based Personal Computer\u201d, Journal of Embedded Computing, pp 107 \u2013 116, 2012<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, <strong>E. John<\/strong>, and B. Lee, \u201cReducing Thermal Hotspots in Microprocessors with Expanded Component Sizing\u201d, IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) 2012, Boise, Idaho, 635-638 pp.<\/li>\n<\/ul>\n<ul>\n<li>J. Fisher, C. Romo, <strong>E. John<\/strong>, and W. Lin, &#8220;Design and Low Power Implementation of a Reorder Buffer&#8221;, The 2012 International Conference on Computer Design (CDES&#8217;12), pp 22 &#8211; 28, Las Vegas, NV, 2012.<\/li>\n<\/ul>\n<ul>\n<li>R. Arun and\u00a0\u00a0<strong>E. John<\/strong>, &#8220;Performance Bound Energy Efficient L2 Cache Organization for Emerging Workload for Multi-Core Processor:\u00a0 A Comparison of Private and Shared Cache&#8221;,\u00a0 The 2012 International Conference on Computer Design (CDES&#8217;12), pp 103 &#8211; 108, Las Vegas, NV, 2012.<\/li>\n<\/ul>\n<ul>\n<li>J. Luo, K. Morales, B. K. Lee, <strong>E. John<\/strong> and Y. K. Choi, \u201cPerformance-Sensitivity and Performance-Similarity Based Workload Reduction,\u201d 31st IEEE International Performance Computing and Communications Conference (IEEE IPCCC), December 2012<\/li>\n<\/ul>\n<ul>\n<li>A. Camacho, <strong>E. John<\/strong> and R. Krishnan, \u201cDesign and Low Power VLSI Implementation of Triple-DES Algorithm\u201d, in the Proceedings The 2012 International Conference on Security and Management (SAM&#8217;12), Las Vegas, NV, July 16-19, 2012<\/li>\n<\/ul>\n<ul>\n<li>R. Krishnan, <strong>E. John<\/strong> and M. Panday, Towards Security Policy and Architecture for Managing Implantable Medical Devices, in the Proceedings of the The 2012 International Conference on Security and Management (SAM&#8217;12) 2012 Las Vegas NV, July 16-19, 2012.<\/li>\n<\/ul>\n<ul>\n<li>T. Nagaraju, C. Douglas, W. Lin and <strong>E. John<\/strong>, \u201cEffective Dispatching for Simultaneous Multi-Threading (SMT) Processors by Capping Per-Thread Resource Utilization\u201d, The Computing Science and Technology International Journal, Vol. 1, No. 2, December 2011.<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, C. Romo, <strong>E. John<\/strong>, and W. Lin, &#8220;Reducing Thermal Hotspots in Multi-Core Processors Using Dynamic Core Scheduling&#8221;, The 2011 International Conference on Computer Design. (CDES&#8217;11), pp 125 &#8211; 130, Las Vegas, NV, 2011.<\/li>\n<\/ul>\n<ul>\n<li>N. Davanam, H. Y. Kim, B. K. Lee and <strong>E. John<\/strong>, &#8220;Sensitivity Analysis on Hardware Resources in SMT Processors,&#8221; The 2011 International Conference on Computer Design (CDES&#8217;11), 2011<\/li>\n<\/ul>\n<ul>\n<li>C. Romo, S. Eratne, <strong>E. John<\/strong>, and B. K. Lee, &#8220;Leakage &#8211; Delay Tradeoff in Wide-Bit Nanoscale CMOS Adders&#8221;, The 2011 International Conference on Computer Design. (CDES&#8217;11), 146 \u2013 149, Las Vegas, NV, 2011.<\/li>\n<\/ul>\n<ul>\n<li>Binu. P. John, A. Agrawal, B. Steigerwald and <strong>E. John<\/strong>, \u201cImpact of Operating System Behavior on Battery Life\u201d.\u00a0 Journal of Low Power Electronics. Volume 6, Number 1, pp. 10-17, April 2010.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, Eratne, and <strong>E. John<\/strong>, &#8220;A Quasi-Power-Gated Low-Leakage Stable SRAM Cell&#8221;, 53rd IEEE Midwest Symposium on Circuits and Systems, Seattle, WA, 2010<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, P. Nair, and <strong>E. John<\/strong>, &#8220;Leakage Control in Full Adders with Selectively Stacked Inverters&#8221;, 53rd IEEE Midwest Symposium on Circuits and Systems, Seattle, WA, 2010<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, C. Romo, <strong>E. John<\/strong>, and Byeong K Lee, &#8220;Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors&#8221;, The 2010 International Conference on Computer Design (CDES&#8217;10), July 2010, Las Vegas, NV, 2010<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, C. Romo, and <strong>E. John<\/strong>, \u201cLeakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase&#8221;, The 2010 International Conference on Computer Design (CDES&#8217;10), July 2010, Las Vegas, NV, 2010<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, C. Romo, and <strong>E. John<\/strong>, &#8220;Use of Increased Transistor Gate Length for Leakage Reduction in Caches&#8221;, 53rd IEEE Mid-West Symposium on Circuits and Systems, Seattle, WA, 2010<\/li>\n<\/ul>\n<ul>\n<li>Byeong Kil Lee, S. Raghunath and <strong>E. John<\/strong>, &#8220;Architectural Sensitivity Analysis on Network Workloads,&#8221; The 2010 International Conference on Computer Design (CDES&#8217;10), July 2010, Las Vegas, NV, 2010.<\/li>\n<\/ul>\n<ul>\n<li>C. Martinez, M. Pinnamaneni and <strong>E. John<\/strong> &#8220;Performance of Commercial Multimedia Workloads on the Intel Pentium 4: A Case Study&#8221;, International Journal of Computers and Electrical Engineering, Vol. 35, No.1, pp 18 \u2013 32, January 2009.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E. John<\/strong> \u201cImplications of Gated-Vss Technique on Leakage Power in Embedded Caches\u201d, International Journal of Embedded Systems, Vol 4, No.1, pp 17 \u2013 26, 2009.<\/li>\n<\/ul>\n<ul>\n<li>B. P. John, P.S. Nair, <strong>E. John<\/strong> and F. Hudson, \u201cPerformance Measurement of Single, Dual and Quad Core Machines using SPEC CPU 2006\u201d, Proceedings of the International Conference on Computer Design, CDES \u201909, Las Vegas, pp. 143-149, July 2009.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, S. Koppa, <strong>E. John<\/strong> and D. Kudithipudi \u201cTopology Selection of FPGA Look-up Tables for Low-Leakage Operation\u201d The 19th European Conference on Circuit Theory and Design (ECCTD 09), pp 73-76, Turkey, August 2009.<\/li>\n<\/ul>\n<ul>\n<li>C. Isen, L. John and <strong>E. John<\/strong>, \u201cA Tale of Two Processors: Revisiting the RISC-CISC Debate \u201c. 2009 SPEC Benchmark Workshop, Springer, Lecture Notes in Computer Science LNCS 5419, pp. 57-76, January 2009.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, S. Koppa, <strong>E. John<\/strong>, \u201c A Comparative Analysis of Coarse-grain and Fine grain Power Gating for FPGA Lookup Tables\u201d, 52nd IEEE International Midwest Symposium on Circuits and Systems (IEEE-MWSCAS\u201909), pp. 507 \u2013 510, August 2009.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi, S. Petko and <strong>E. John<\/strong> \u201cCache Design for Multimedia Workloads: Power and Energy Tradeoffs\u201d, IEEE Transactions on Multimedia, Vol. 10, No. 6, pp. 1013 \u2013 1021 October, 2008.<\/li>\n<\/ul>\n<ul>\n<li>C. B. Smith, D. R. Mandel and <strong>E. John<\/strong>, \u201cA Superscalar Simulation Employing Poisson Distributed Stalls\u201d, International Journal of Computers and Electrical Engineering, pp. 192 \u2013 201,Vol. 34, No. 3, May 2008.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi, and <strong>E. John<\/strong>, &#8220;On Estimation of Static Power-Performance in TCAM\u201d 51st IEEE Midwest Symposium on Circuits and Systems, pp.783-786 MWSCAS\u201908, August 10 \u2013 13, 2008.<\/li>\n<\/ul>\n<ul>\n<li>A. Hussein, H. Saleh, B. Mohammad, and <strong>E. John<\/strong>, &#8220;Optimum Organization of SRAM-based Memory for Leakage Power Reduction\u201d 51st IEEE Midwest Symposium on Circuits and Systems, pp.775-778 MWSCAS\u201908, August 10 \u2013 13, 2008.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, S. Eratne, and <strong>E. John<\/strong>, \u201cTopology-related effects of Gated-Vdd and Gated Vss techniques on full-adder Leakage and Delay at 65nm and 45 nm\u201d, in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS &#8217;08), 2008, pp. 972-975.<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, S. Puthenpurayil, <strong>E. John<\/strong>, &#8220;Energy Efficient Lossless Image Compression,&#8221; in 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 2008, pp. 344-347<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, S. K. K. Venkataswamy, S. Eratne and E. John, \u201cImpact of High-K Dielectric Transistors on Full-Adder Delay and Leakage Characteristics\u201d, in Proc. IASTED Int. Conf. Circuits and Systems (CS &#8217;08), 2008, pp. 55-60.<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, S. Puthenpurayil, <strong>E. John<\/strong>, &#8220;Energy Efficiency of Data Compression with Wavelets&#8221;, 2008 International Conference on Image Processing, Computer Vision, and Pattern Recognition WORLDCOMP&#8217;08, Las Vegas, NV, 2008<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, S. Eratne, <strong>E. John<\/strong>, &#8220;Effects of Register File Organization on Leakage Power Consumption,&#8221; 2008 International Conference on Computer Design WORLDCOMP&#8217;08, Las Vegas, NV, 2008<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair and <strong>E. John<\/strong>, \u201cAnalyzing the Performance of Personal Computers based on Intel microprocessors for Sequence Aligning Bioinformatics Applications\u201d International Journal of Bioinformatics Research and Applications, Vol. 3, No.2, pp. 187-205, 2007<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E. John<\/strong>, \u201cStatic Power Analysis and Estimation in TCAM cells\u201d, Journal of Low Power Electronics, Vol. 3, pp. 293 \u2013 301, 2007<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, P. Nair and <strong>E. John<\/strong>, &#8220;Leakage current control of nanoscale full adder cells using input vectors&#8221;, IEEE International Conference on Design &amp; Technology of\u00a0\u00a0 Integrated Systems, pp. 185 \u2013 189, DTIS\u201907, Rabat, Morocco, September\u00a0\u00a0 2007.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi, P. Nair and <strong>E. John<\/strong>, &#8220;On Estimation and Optimization of Leakage Power in CMOS Multipliers&#8221; IEEE Midwest Symposium on Circuits and Systems, MWSCAS\u201907, August 2007.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair and <strong>E. John<\/strong>, &#8220;Performance Analysis of an Intel Pentium-4-based Personal Computer for Multiple Sequence Alignment&#8221; International Conference on Computer Design, CDES\u201907, Las Vegas, NV, June 2007.<\/li>\n<\/ul>\n<ul>\n<li>B. K. Lee, L. K. John and <strong>E. John<\/strong>, \u201cArchitectural Enhancements for Network Congestion Control Applications\u201d IEEE Transactions on VLSI Systems, Vol. 14, No. 6, pp. 609-615, June, 2006<\/li>\n<\/ul>\n<ul>\n<li>R. Valliyappan, <strong>E. John<\/strong>, R. Kuzet, and H. Foltz \u201cLow Power RF CMOS Receiver Front-end Using Reflex Amplifier\u201d The International Signal Processing Conference, Santa Clara, California, October 30-November 2, 2006.<\/li>\n<\/ul>\n<ul>\n<li>N. Marupudi, <strong>E. John<\/strong> and F. Hudson, \u201cFingerprint Verification Based on Image Filtering of Ridges\u201d The International Signal Processing Conference, Santa Clara, California, October 30-November 2, 2006.<\/li>\n<\/ul>\n<ul>\n<li>J. Tang, F. Hudson and <strong>E. John<\/strong>, \u201cRemote Fingerprint Entry Verification Using Bluetooth Wireless Technology\u201d The International Signal Processing Conference, Santa Clara, California, October 30-November 2, 2006.<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, D. Kudithipudi, <strong>E. John<\/strong> and F. Hudson, \u201cPerformance Analysis of Embedded Applications on a Pentium-4 Based Machine\u201d ESA&#8217;06 &#8211; The 2006 International Conference on Embedded Systems &amp; Applications, Las Vegas, Nevada, June 26-29, 2006<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair and <strong>E. John<\/strong>, \u201cPerformance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study\u201d BIOCOMP&#8217;06- The 2006 International Conference on Bioinformatics &amp; Computational Biology, Las Vegas, Nevada, June 26-29, 2006<\/li>\n<\/ul>\n<ul>\n<li>Ryan Sweet, Pradeep Nair and <strong>E.<\/strong> <strong>John<\/strong>, \u201cImpact of Input Vectors on Leakage Current in nanoscale Complimentary MOS Gates\u201d, UTSA Engineering, Science and Biotechnology Student Conference, San Antonio, November 2006<\/li>\n<\/ul>\n<ul>\n<li>C. Martinez, M. Pinnamaneni and <strong>E. John<\/strong>, \u201cMultimedia Workloads versus SPEC CPU2000\u201d, 2006 SPEC Benchmark Workshop, Austin, TX, January 23, 2006<\/li>\n<\/ul>\n<ul>\n<li>P. S. Nair, D. Kudithipudi and <strong>E. John<\/strong>, \u201cDesign and Implementation of a CMOS Non-Restoring Divider\u201d, IEEE Region 5 Conference, San Antonio, TX, April 6- 8, 2006<\/li>\n<\/ul>\n<ul>\n<li>N. Marupudi, <strong>E. John<\/strong> and F. Hudson \u201cFingerprint Verification in Multimodal Biometrics\u201d, IEEE Region 5 Conference, San Antonio, TX, April 6- 8, 2006.<\/li>\n<\/ul>\n<ul>\n<li>S. Eratne, D. Kudithipudi and <strong>E. John<\/strong>, \u201cPerformance Analysis of Full Adders in Nanoscale CMOS Design\u201d, IEEE Region 5 Conference, San Antonio, TX, April 6- 8, 2006<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E. John<\/strong> &#8220;Implementation of Low Power Digital Multipliers using 10 Transistor Adder Blocks&#8221;, <em>Journal of Low Power Electronics<\/em>, Vol. 1, pp. 286 \u2013 296, 2005<\/li>\n<\/ul>\n<ul>\n<li>R. Kuzet, M. Chilikuri, H. Foltz and <strong>E. John<\/strong>, \u201cRF CMOS Self-Oscillating Gilbert Cell Mixer\u201d, Proceedings of\u00a0 IASTED International Conference on Circuits, Signals, and Systems (CSS 2005), October 24 &#8211; 26, 2005, in Marina Del Rey, USA<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E. John<\/strong>, &#8220;Parametrical Characterization of Leakage Power in Embedded System Caches using Gated-Vss&#8221;, Proceedings of International Association of Science and Technology for Development on Circuits, Signals and Systems, Marina Del Rey, October 2005<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E. John<\/strong>, &#8220;A Combinatorial Approach to Suppress Leakage in Nanoscale SRAM Cells&#8221;, in the proceedings of\u00a0 IEEE Midwest Symposium on Circuits and Systems-2005, Cincinnati, Ohio, August 2005.<\/li>\n<\/ul>\n<ul>\n<li>B. K. Lee, L. K. John and <strong>E. John<\/strong>,\u00a0 \u201cArchitectural Support for Accelerating Congestion Control Applications in Network Processors\u201d IEEE 16th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2005). Greece, July 2005.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E.John<\/strong>, &#8220;A Framework to Moderate Leakage Power in Nanoscale CMOS SoC Devices&#8221;, Poster Presentation, NanoSummit Research Conference, Houston,\u00a0 July 2005.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi and <strong>E. John<\/strong>, &#8220;Parametrical Characterization of leakage power in Nanoscale Technologies&#8221;, Poster Presentation, IBM&#8217;s Austin Conference on Energy Efficient Design, March 2005.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi, S. Petko and <strong>E. John<\/strong>, \u201cCache leakage power Analysis in Embedded Application\u201d in proceedings of IEEE Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Vol. II, pp. 517-520, 2004.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi, R. Kota, <strong>E. John<\/strong> and Z. P. Tanner, \u201cImpact of Nanotechnology on the Performance of CMOS Digital Multilpliers\u201d, in the Proceedings of International Conference on Circuits, Signals and Systems, IASTED 2004, Clearwater Beach, FL, November 2004.<\/li>\n<\/ul>\n<ul>\n<li>D. Kudithipudi, R. Kota, <strong>E. John<\/strong> and Z. P. Tanner, \u201cPower, Area and Delay Performance Comparison of Multipliers for Embedded Systems\u201d in the Proceedings of International Signal Processing Conference, San Jose, California, Oct, 2004<\/li>\n<\/ul>\n<ul>\n<li>R. Kuzet, M. Chilikuri, S. Puthenpurayil, H. Foltz and <strong>E. John<\/strong>, \u201cRF CMOS receiver Front-End Using Reflex Amplifier\u201d Proceedings of IASTED International Conference on Communication Systems and Applications (CSA), Banff, AB, Canada &#8211; July 8-10, 2004<\/li>\n<\/ul>\n<ul>\n<li>S. Petko, D. Kudithipudi and <strong>E. John<\/strong>, \u201cMemory System Characterization for Multimedia Applications\u201d International Signal Processing Conference (ISPC), Dallas, TX. March 31 \u2013 April 3, 2003<\/li>\n<\/ul>\n<ul>\n<li>M. Wasiewicz, D. Kudithipudi and <strong>E. John<\/strong> \u201cLow Power Parallel Digital Multipliers using 10 Transistor Adder Circuits\u201d International Signal Processing Conference (ISPC), Dallas, TX. March 31 \u2013 April 3, 2003<\/li>\n<\/ul>\n<ul>\n<li>A. K. Ojha, and <strong>E. John<\/strong>, \u201cA Paradigm for Testing RISC Processor \u2013Based Complex System\u2013on-Chip (SOC),\u201d Proc. of the IEEE Southeastcon 2003, Ocho Rios, Jamaica, March 2003.<\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong>, S. Petko, L. John and J. Law, \u201cAccess Time and Energy Tradeoffs for Caches in High Frequency Microprocessors\u201d in Proceedings of 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August, 2002.<\/li>\n<\/ul>\n<ul>\n<li>S. Petko, D. Kudithipudi and <strong>E. John<\/strong>, \u201cCache performance of Video Computation Workloads\u201d Proceedings of the International Workshop on Digital and Computational Video, Clearwater, FL, November 2002.<\/li>\n<\/ul>\n<ul>\n<li>A. Moreno and <strong>E. John<\/strong>, \u201cA Flexible Design for Timing Signals Generation for the Conversion of Computer Video Formats to SDTV 480P\u201d, IEEE Transactions on Consumer Electronics pp.1081-1086, Vol. 45, November 1999.<\/li>\n<\/ul>\n<ul>\n<li>R. Shalem, <strong>E. John<\/strong> and L. John, \u201cA Novel Low Power Energy Recovery Full Adder Cell\u201d Proceedings of the Great Lake Symposium on VLSI, pp. 380-383, 1999<\/li>\n<\/ul>\n<ul>\n<li>M. Rodriguez and <strong>E. John<\/strong>, \u201cDesign and VLSI Implementation of Arithmetic Circuits\u201d, Proceedings of the ASEE\/GSW Conference, 1999.<\/li>\n<\/ul>\n<ul>\n<li>L. K. John and <strong>E. John<\/strong>, &#8220;A Dynamically Reconfigurable Interconnect for Array Processors&#8221;, IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 150-157, March 1998.<\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong>, F. Hudson and L. Kurian &#8220;Hybrid Tree: A Scalable Optoelectronic Interconnection Network for Parallel Computing&#8221; Proceedings of the 31st\u00a0 Hawaii International Conference on System Sciences, Vol. VII, pp. 466-474, January 1998.<\/li>\n<\/ul>\n<ul>\n<li>H. Saenz and <strong>E. John<\/strong>, &#8220;Design and FPGA Implementation of an 8-bit Processor&#8221;,pp.228- 233, Proceedings of the ASEE\/GSW Conference, 1998.<\/li>\n<\/ul>\n<ul>\n<li>L. Roitberg and <strong>E. John<\/strong> &#8221; Voice Recognition Hardware Interface Using Field Programmable Gate Arrays&#8221;\u00a0 pp.230-233,\u00a0 Proceedings of the ASEE\/GSW Conference, 1997.<\/li>\n<\/ul>\n<ul>\n<li>E. Lott and <strong>E. John<\/strong> &#8221; Design and Simulation of Solid state Semiconductor Devices\u201d pp.222-225,\u00a0 Proceedings of the ASEE\/GSW Conference, 1997.<\/li>\n<\/ul>\n<ul>\n<li>D. Ault, B. Lozano and <strong>E. John<\/strong> &#8220;3-D Graphics Computation using Field Programmable Gate Arrays&#8221; pp.226-229, Proceedings of the ASEE\/GSW Conference, 1997.<\/li>\n<\/ul>\n<ul>\n<li>P. T. Hulina, L. D. Coraor, L. Kurian, and <strong>E. John<\/strong>, \u201cDesign and VLSI Implementation of an Address Generation Coprocessor\u201d, IEE Proceedings on Computers and Digital Techniques, Vol 142, No. 2, pp. 145- 151, March 1995.<\/li>\n<\/ul>\n<ul>\n<li>M. B. Das, J. W. Chen, and <strong>E. John<\/strong>, \u201cDesign of Optoelectronic Integrated Circuit Receivers for High Sensitivity and Maximally Flat Frequency Response\u201d, IEEE\/OSA Journal of Lightwave Technology, Vol. 13, No.9, pp. 1876-1884, 1995.<\/li>\n<\/ul>\n<ul>\n<li>L. Kurian, D. Brewer, <strong>E. John<\/strong>, \u201cDesign of a Highly Reconfigurable Interconnect for Array Processors\u201d, Proceedings of the 8th International Conference on VLSI Design, pp. 321-325, January 1995.<\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong>, M. B. Das, W-Y. Yang, T.S. Miller, and D. Miller \u201c Fabrication and Performance of a Novel Ultra-Low Capacitance MSM Photodetector for High Speed OEIC Receiver Applications\u201d Proceedings of the 7th International Conference on InP and Related Materials, May 9-13, 1995, Sapporo, Japan.<\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong> and M. B. Das, \u201cDesign and Performance Analysis of InP-Based High-Speed and High Sensitivity Optoelectronic Integrated Receivers\u201d, IEEE Transactions on Electron Devices, Vol. 42, No. 2, pp. 162-172, 1994.<\/li>\n<\/ul>\n<p><strong>E. John<\/strong> and M. B. Das, \u201cA New Design Approach for a High Transimpedance and Low-Noise Optoelectronic Integrated Lightwave Receiver with 24GHz Bandwidth\u201d Microwave and Optical Technology Letters, Vol. 7, No.6, pp. 259-262, April 1994.<\/p>\n<ul>\n<li><strong>E. John<\/strong> and M.B. Das, \u201cCircuit Optimization of Optoelectronic Integrated Lightwave Receivers for Maximum Bandwidth and High-Sensitivity\u201d, Proceedings of the Conference on Emerging Optoelectronic Technologies, 18-22, July 1994.<\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong>, M. B. Das, Y. W. Yang, and S. M. J. Liu \u201cExtraction of High Frequency Equivalent Network Parameters of HBT\u2019s by Low Frequency Extrapolation of Microwave S-Parameter Data\u201d Proceedings of the 14th IEEE\/ Cornel Conference on High-Speed Semiconductor Devices and Circuits, pp 141-147, 1993.<\/li>\n<\/ul>\n<ul>\n<li>P. T. Hulina, L. Kurian, <strong>E. John<\/strong> and L. D. Coraor, \u201cDesign and VLSI Implementation of an Access Processor for a Decoupled Architecture\u201d, Journal of Microprocessors and Microsystems, Vol. 16, No. 5, pp. 237-247, May 1992.<\/li>\n<\/ul>\n<ul>\n<li><strong>E. John<\/strong> and M. B. Das, \u201cSpeed and Sensitivity Limitations of Optoelectronic Receivers\u00a0 Based on MSM Photodiode and Millimeter Wave HBTs on InP Substrate\u201d, IEEE Photonics Technology Letters, vol. 4, No. 10, pp 1145-1148, 1992.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Granted Patents: US Patent # 12,261,937, Mar 2025: &#8220;Method &amp; Apparatus for an Ultra Low Power VLSI Implementation of the 128-Bit AES Algorithm Using a Novel Approach to the Shiftrow Transformation&#8221;, (Additional claims on Patent # 11,948,596) A. Muthineni and E. John US Patent # 12,094,243, Sep 2024, &#8220;Method and Apparatus for Discreet Facial Recognition &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/ceid.utsa.edu\/ejohn\/publications\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Publications&#8221;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":87,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-14","page","type-page","status-publish","has-post-thumbnail","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.5 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Publications - Eugene John<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ceid.utsa.edu\/ejohn\/publications\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Publications - Eugene John\" \/>\n<meta property=\"og:description\" content=\"Granted Patents: US Patent # 12,261,937, Mar 2025: &#8220;Method &amp; Apparatus for an Ultra Low Power VLSI Implementation of the 128-Bit AES Algorithm Using a Novel Approach to the Shiftrow Transformation&#8221;, (Additional claims on Patent # 11,948,596) A. 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Muthineni and E. John US Patent # 12,094,243, Sep 2024, &#8220;Method and Apparatus for Discreet Facial Recognition &hellip; Continue reading \"Publications\"","og_url":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/","og_site_name":"Eugene John","article_modified_time":"2026-04-17T00:19:44+00:00","og_image":[{"width":1920,"height":500,"url":"https:\/\/ceid.utsa.edu\/ejohn\/wp-content\/uploads\/sites\/18\/2017\/07\/utsa-orange-bar.jpg","type":"image\/jpeg"}],"twitter_card":"summary_large_image","twitter_misc":{"Est. reading time":"29 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/","url":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/","name":"Publications - Eugene John","isPartOf":{"@id":"https:\/\/ceid.utsa.edu\/ejohn\/#website"},"primaryImageOfPage":{"@id":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/#primaryimage"},"image":{"@id":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/#primaryimage"},"thumbnailUrl":"https:\/\/ceid.utsa.edu\/ejohn\/wp-content\/uploads\/sites\/18\/2017\/07\/utsa-orange-bar.jpg","datePublished":"2017-07-07T20:21:07+00:00","dateModified":"2026-04-17T00:19:44+00:00","breadcrumb":{"@id":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/ceid.utsa.edu\/ejohn\/publications\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/#primaryimage","url":"https:\/\/ceid.utsa.edu\/ejohn\/wp-content\/uploads\/sites\/18\/2017\/07\/utsa-orange-bar.jpg","contentUrl":"https:\/\/ceid.utsa.edu\/ejohn\/wp-content\/uploads\/sites\/18\/2017\/07\/utsa-orange-bar.jpg","width":1920,"height":500},{"@type":"BreadcrumbList","@id":"https:\/\/ceid.utsa.edu\/ejohn\/publications\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/ceid.utsa.edu\/ejohn\/"},{"@type":"ListItem","position":2,"name":"Publications"}]},{"@type":"WebSite","@id":"https:\/\/ceid.utsa.edu\/ejohn\/#website","url":"https:\/\/ceid.utsa.edu\/ejohn\/","name":"Eugene John","description":"Department of Electrical and Computer Engineering ","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/ceid.utsa.edu\/ejohn\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"}]}},"_links":{"self":[{"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/pages\/14","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/comments?post=14"}],"version-history":[{"count":0,"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/pages\/14\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/media\/87"}],"wp:attachment":[{"href":"https:\/\/ceid.utsa.edu\/ejohn\/wp-json\/wp\/v2\/media?parent=14"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}