Eugene John

/ / Published in
Professor
AET 2.358
210-458-5590
eugene.john@utsa.edu
https://ceid.utsa.edu/ejohn/
 

Areas of Teaching Interest

VLSI Design, Topics in VLSI Design, Computer Architecture, Topics in Computer Architecture

Areas of Research Interest

Energy Efficient Computing, Ultra-Low Energy Computing for Implantable Cardiac Devices, Efficient Hardware for Machine Learning and Artificial Intelligence, Integrated Circuit IP Security and Trust, Hardware Security, Low Power VLSI Circuits and Systems, Power-Aware and Secure Systems, Power Aware Cloud Computing, Computer Architecture and Performance Evaluation.

Educational Background

Ph.D, Pennsylvania State University

Selected Publications

  • S. Verma, Q. Wu, B. Hanindhito, G. Jha, E. John, R. Radhakrishnan and L. K. John, “Demystifying the MLPerf Training Benchmark Suite”, (accepted), In the Proc. of the 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’20), Boston, MA, August 2020.
  • T. Banerjee, E. Adib, A. Taha and E. John, “Sequential methods for detecting a change in the distribution of an episodic process,” (accepted) In the Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Barcelona, Spain, May 2020.
  • T. K. Kodali, Y. Zhang, E. John and W. Lin, “An Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction”, Journal of Information Science and Engineering, pp 1-12, Jan 2020.
  • S. Mostafa and E. John, “Resource Shared Galois Field Computation for Energy Efficient AES/CRC in IoT Applications”, IEEE Transactions on Sustainable Computing, pp. 340-348, vol. 4, Dec. 2019.
  • A. Owahid, and E. John “Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction”, 31st International Symposium on Computer Architecture and High-Performance Computing, SBAC-PAD 2019, October 15-18 – Campo Grande, MS, Brazil.
  • C. Davis, A. Muthineni, and E. John, “Low-Power Advanced Encryption Standard for Implantable Cardiac Devices”, 62nd IEEE International Midwest Symposium on Circuits and Systems, Dallas, TX, Aug. 4-7, 2019.
  • S. Mostafa, E. John and M. Panday, “Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers”, IEEE Transactions on VLSI Systems, Vol. 27. No. 4, pp. 983- 987, 2019.
  • L. John, S. Verma, Q. Wu, B. Hanindhito, R. Radhakrishnan, G, Jha and E. John,” Demystifying Hardware Infrastructure Choices for Deep Learning using MLPref”, NVIDIA GPU Technology Conference (GTC-2019), San Jose, CA, March 2019.
  • S. Verma, Q. Wu, B. Hanindhito, G. Jha, E. John, R. Radhakrishnan, and L. K. John,”Metrics for Machine Learning Workload Benchmarking”, International Workshop on Performance Analysis of Machine Learning Systems (FastPath) in conjunction with ISPASS 2019. March 2019.
  • J. Whitehouse, Q. Wu, S. Song, E. John, A. Gerstlauer, and L. K. John, “A Study of Core Utilization and Residency in Heterogeneous Smartphone Architectures”, ACM International Conference on Performance Engineering (ICPE). April 2019.
  • A. Owahid, and E. John, “Wasted Dynamic Power and Correlation to Instruction Set Architecture for CPU Throttling” The Journal of Supercomputing, pp. 2436-2454, Volume 75, Number 5, May 2019.
  • E. Tolliver and E. John, “Power Reduction in CNNs by Modifying Floating Point Number Format for Machine Learning” 4th Annual Samsung Austin Research Center Technology Forum, Austin, TX, Oct 16, 2018.
  • J. Portillo and E. John, “Using Static Hardware Wrappers to Thwart Hardware Trojans and Code Bugs at Runtime”, 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada, August 5th-8th, 2018.
  • G. Jha and E. John, “Performance Analysis of Single-Precision Floating-Point MAC for Deep Learning”, 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada, August 5th-8th, 2018.
  • T. A. Newton and E. John, “A Metric for Measuring Power Efficiency and Data Throughput in Mobile ad hoc Networks”, International Journal of Parallel, Emergent and Distributed Systems, 2018.
  • S. Koppa and E. John, “Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices”, Journal of Low Power Electronics, Vol. 14, pp.,18– 27, March, 2018.
  • J. Portillo and E. John, “Detecting Vulnerabilities within Black Boxed CPUs using Assertion Based Verification for Enhanced Security”, The 2018 International Conference on Security and Management (SAM’18), Las Vegas, July 30 – August 2, 2018.
  • S. Nanduru, S. Koppa and E. John, “An Ultra-Low Power Robust Kogge-Stone Adder at Sub-Threshold Voltages for Implantable Bio-Medical Devices”, International Journal of VLSI Design & Communication Systems (VLSICS), pp. 1 – 13, Vol.8, No.6, December 2017.
  • J. Portillo and E. John, “Enhancing Trojan Detection by Finding LTL and Taint Properties in RTL Circuit Designs: A Case Study”, The 2017 International Symposium on Cyber Warfare, Cyber Defense, and Cyber Security, Las Vegas, NV, 14 – 16, Dec 2017.
  • Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin and John, “FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance”, ACM Transactions on Embedded Computing Systems (TECS), 2017.