Wei-Ming Lin

Areas of Teaching Interest

Digital Systems Design, Computer Architecture, Computer Arithmatic, Distributed Computing, Parallel Processing

Areas of Research Interest

High-Performance Computing, Computer Architecture, Parallel Processing, Autonomous Performance Optimization, Computer Network, Digital System Design

Educational Background

Ph.D., University of Southern California, 1991.

Selected Publications

• Tarak K. Kodali, Yilin Zhang, Eugene John and Wei-Ming Lin, “An Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction”, Journal of Information Science and Engineering, Vol. 36, No. 1, 2020, pp 1-12.
• Shane Carrol and Wei-Ming Lin, “Applied On-Chip Machine Learning for Dynamic Resource Control in Multithreaded Processors”, Parallel Processing Letters (PPL), Vol. 29, No. 3,
• Marwa Naveed Sheikh and Wei-Ming Lin, “Dynamic Capping of Rename Registers for SMT Processors”, Journal of Systems Architecture, 99, October, 2019, 101637.
• Wenjun Wang and Wei-Ming Lin, “Real-Time Physical Register File Allocation with Neural Networks for Simultaneous Multi-Threading Processors”, International Journal of High Performance Systems Architecture, 8, No. 3, 2019.
• Shane Carrol and Wei-Ming Lin, “Round Robin Thread Selection Optimization in Multithreaded Processors”, Parallel Processing Letters (PPL), 29, Issue No. 1, March 2019.
• Shane Carrol and Wei-Ming Lin, “A Queuing Model for CPU Functional Unit and Issue Queue Configuration”, Simulation Modelling Practice and Theory, 87, pp. 327-342, September 2018.
• Wenjun Wang and Wei-Ming Lin, “An Integrated Autonomous Control Mechanism to Optimize Sharing of Multiple Resources in Simultaneous Multi- Threading Processors”, Journal of Systems Architecture, Vol. 88, pp. 87-96, August
• Wenjun Wang and Wei-Ming Lin, “System Performance Enhancement with Thread Suspension for Simultaneous Multi-Threading Processors”, International Journal of Computers and Applications, DOI: 10.1080/1206212X.2018.1489572, June,
• Madhava K. Ramanathan and Wei-Ming Lin, “A Controlled Fetching Technique for Effective Management of Shared Resources in SMT Processors”, Microprocessors and Microsystems (MICPRO2649), Vol. 57, pp. 42-51, March 2018.
• Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin and Eugene John, “FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance”, ACM Transactions on Embedded Computing Systems (TECS), Vol. 16, Issue 5, September,
• Madhava K. Ramanathan and Wei-Ming Lin, “An Intelligent Fetching algorithm for Efficient Physical Register File Allocation in Simultaneous Multi-Threading CPUs”, International Journal of Computer Systems (ISSN: 2394-1065), Vol. 4, Issue 4, April,
• Yilin Zhang and Wei-Ming Lin, “An Intelligent Resource Sharing Protocol on Write Buffers in Simultaneous Multi-Threading Processors”, IOSR Journal of Computer Engineering, Vol. 18, Issue 6, December
• Wenjun Wang and Wei-Ming Lin, “Performance Enhancement with Speculative- Trace Capping at Different Pipeline Stages in Simultaneous Multi-Threading Processors”, Computer Applications: An International Journal (CAIJ), Vol. 3, 4, November 2016.
• Yilin Zhang and Wei-Ming Lin, “Improving Resource Utilization by Curbing Speculative Trace Progression in Simultaneous Multi-Threading CPUs”, Journal of Information Science and Engineering, Vol. 32, No. 6, November
• Yilin Zhang and Wei-Ming Lin, “Efficient Resource Sharing Algorithm for Physical Register File in Simultaneous Multi-Threading Processors”, Microprocessors and Microsystems, doi:10.1016/j.micpro.2016.06.002, July, 2016.
• Shane Carroll and Wei-Ming Lin, “Latency-Aware Write Buffer Resource Control in Multithreaded Cores”, International Journal of Distributed and Parallel Systems (IJDPS), Vol. 7, Number 1, January
• Yilin Zhang, and Wei-Ming Lin, “Autonomous Issue Queue Distribution Control for Simultaneous Multi-Threading CPUs”, Journal of Emerging Trends in Computing and Information Sciences, Vol. 6 No. 12, December
• Sherifdeen Lawal, Yilin Zhang, Wei-Ming Lin, “Prioritizing Write Buffer Occupancy in Simultaneous Multithreading Processors”, Journal of Emerging Trends in Computing and Information Sciences, Vol. 6, 10, pp. 515-522, November 2015.
• Shane Carroll and Wei-Ming Lin, “Dynamic Issue Queue Allocation Based on Reorder Buffer Instruction Status”, International Journal of Computer Systems (IJCS), Vol. 2, Issue 9, pp. 395-404, September,
• Samir Talegaon and Wei-Ming Lin, “Selective Context Blocking after Branch Performance Evaluation for Improving SMT Performance”, Computer Applications: An International Journal (CAIJ), August 2014, Vol. 1, Number