US Patent # 11,948,596, April 2024, “Method and Apparatus for Defending Against Laser or Other Electromagnetic Wave-Based Audio Injection Attacks on Voice-Controllable Devices and Systems”. E. John and R. Krishnan.
US Patent # 11,838,403, Dec 2023: “Method & Apparatus for an Ultra Low Power VLSI Implementation of the 128-Bit AES Algorithm Using a Novel Approach to the Shiftrow Transformation”, A. Muthineni and E. John.
US Patent # 10,891,110, Jan, 2021: “AES/CRC Engine Based on Resource Shared Galois Field Computation” S. Mostafa and E. John.
US Patent # 10,359,832, July, 2019: “Method and Apparatus for Reducing Power and Cycle Requirement for FFT of ECG signals”, E. John and S. Mostafa
US Patent # 8,250,350, August 21, 2012: “Computer systems with non-volatile write-protected memory based operating systems and secure architecture”, E. John, Thomas John and Lizy John.
US Patent # 8,214,629, July 3, 2012: “Computer systems with secure instantly available applications using non-volatile write protected memory”, E. John, Thomas John and Lizy John.
US Patent #6,824,480, November 30, 2004: “Method and apparatus for location of objects, and application to real time display of the position of players, equipment and officials during a sporting event”, E. John and H. Foltz.
Pending Patent Applications
“Method and Apparatus for Discreet Facial Recognition on Pocket-Size Offline Mobile Platform With Augmented Reality Feedback with Real-Time Training Capability for Usage by Universal Users”, P. Stockton and E. John; Application filed on May, 2020.
“Semi-Streaming Data Flow Architecture with Layer-Type Specialized Processing Engines for the Implementation of Convolutional Neural Networks in Hardware.”, N. Shayduk and E. John; Application filed on April, 2021
Book(s):
“Fundamentals of Logic Design”, Enhanced 7th Edition, by Charles H. Roth, Jr., Larry L. Kinney, and Eugene B. John, CENGAGE Learning, Boston, MA. (1/1/2020).
E. John and J. Rubio, “Unique Chips and Systems” edited book; CRC Press, November 2007
Book Chapters:
C. Davis, P. Stockton, Z. Susskind, E. John and L. K. John, “Characterization of Neuro-Symbolic AI and Graph Convolutional Network Workloads”, in Artificial Intelligence: Machine Learning, Convolutional Neural Networks and Large Language Models, Editors: L. Deligiannidis, G. Dimitoglou, H. R. Arabnia, and A. P. Tafti, Publisher: De Gruyter, Berlin, Germany; to be published in January, 2024.
E. John, “Semiconductor Memory Circuits”, in the Computer Engineering Hand Book, 2nd ed. Editor: V. Oklobdzija, CRC Press, pp. 5-1 to 5-27, 2008.
E. John, “VLSI Circuits”, in the Computer Engineering Hand Book, Editor: V. Oklobdzija, CRC Press, pp. 2.1 – 2.20, 2002
L. John and E. John, “Bit-Slice Computers”, in the Encyclopedia of Electrical and Electronics Engineering, Supplement 1, Editor: J.G.Webster, John Wiley and Sons, Inc. pp. 39-44, 1999.
Journal and Conference Publications:
P. Sengupta and E. John “Time Series Pattern Matching Technique for Low-Energy Arrhythmia Classification in Implantable Cardiac Devices” in the proceedings of the 3rd IEEE International Conference on Computing and Machine Intelligence (ICMI-2024). Michigan, April 13-14, 2024.
A. Owahid, and E. John, “Instruction Profiling Based Predictive Throttling for Power and Performance”, in IEEE Transactions on Computers, vol. 72, no. 12, pp. 3532-3545, Dec. 2023.
L. John, F. Franca, S. Mitra, Z. Susskind, P. Lima, I. Miranda, E. John, D. Dutra and M. Breternitz, “Dendrite-inspired Computing to improve Resilience of Neural Networks to Faults in Emerging Memory Technologies”, in the Proceedings of the 8th IEEE International Conference on Rebooting Computing (ICRC 2023), 5-6, December, 2023; San Diego, CA.
P. Stockton, C. Davis and E. John, “Microarchitecture Characterization and Analysis of Emerging Neuro-Symbolic A.I. Workloads”, in the Proceedings of the 2023 International Conference on Computational Science and Computational Intelligence (CSCI’23): December 13-15, 2023; Las Vegas.
C. Davis, P. Stockton and E. John, “Profiling Analysis for Enhancing the Performance of Graph Neural Networks”, in the Proceedings of the 22nd IEEE International Conference on Machine Learning and Applications, December 15-17, 2023, Jacksonville, Florida.
P. Stockton, and E. John, “Neuro-Symbolic Workload Micro-Architecture Analysis and Characterization of the Neural Logic Machine”, SRC (Semiconductor Research Corporation) TECHCON 2023, Austin, Texas, September 10-12, 2023.
Y. Oleyaeimotlagha, T. Banerjee, A. Taha and E. John, “Quickest Change Detection in Statistically Periodic Processes with Unknown Post-Change Distribution”, Sequential Analysis: Design Methods and Applications, Pages 404-437, Dec 2023.
C. Davis, P. Stockton, Z. Susskind, E. John, and Lizy K. John, “Characterization of Emerging AI Workloads: Neural Logic Machines and Graph Convolutional Networks” the 2022 International Conference on Computational Science and Computational Intelligence (CSCI’22), December 14-16, 2022; Las Vegas.
E. Tolliver, V. Pillai, A. Jha and E. John, “A Comparative Analysis of Half Precision Floating Point Representations in MACs for Deep Learning”, in the Proc. of the International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME), 16-18 November 2022, Maldives
S. Aphale, A. Jha, and E. John, “High Accuracy Arrhythmia Classification using Transfer Learning with Fine-Tuning” 2022 IEEE 13th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), Virtual Conference, New York, USA 26 – 29 October, 2022
A. Jha, E. John, and T. Banerjee, “Multi-Class Classification of Dementia from MRI Images Using Transfer Learning” 2022 IEEE 13th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), Virtual Conference, New York, USA 26 – 29 October, 2022
A. Jha, E. John and T. Banerjee,” Transfer Learning for COVID-19 and Pneumonia Detection using Chest X-Rays”, 65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022), Fukuoka, Japan (Virtual Conference), August 7 – 10, 2022.
C. Davis and E. John, “Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices”, 65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022), Fukuoka, Japan (Virtual Conference), August 7 – 10, 2022.
W. Chen, T. Banerjee, E. John, “A Meta-Transfer Learning Approach to ECG Arrhythmia Detection”, the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC), Glasgow, United Kingdom 11-15 July 2022.
S. D. Sakyi, V. Kothavade and E. John, “Breast Cancer Detection using Deep Learning”, Viva Science SA, San Antonio, April 9, 2022 (Poster Session).
Z. Susskind, B. Arden, L. K. John, P. Stockton, and E. B. John, “Characterizing Neuro-Symbolic Workloads”, IBM IEEE CAS/EDS AI Compute Symposium, October 13-14, 2021 (Poster Session).
S. Aphale, E. John and T. Banerjee, “ArrhyNet: A High Accuracy Arrhythmia Classification Convolutional Neural Network”, the 2021 IEEE 64th International Midwest Symposium on Circuits & Systems (MWSCAS 2021), August 9-11, 2021
T. Banerjee, A. Taha and E. John, “Robust Quickest Change Detection in Statistically Periodic Processes”, the 2021 IEEE International Symposium on Information Theory (ISIT-2021), Melbourne, Victoria, Australia, 12-20 July, 2021
Banerjee, S. Padhy, A. Taha and E. John, “Quickest Joint Detection and Classification of Faults in Statistically Periodic Processes, In Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Toronto, Canada, June 2021
N. Shaydyuk and E. John, “FPGA Implementation of MobileNetV2 CNN Model Using Semi-Streaming Architecture for Low Power Inference Applications”, 18th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA-2020), England, UK, 17-19, pp. 160-167, December 2020.
K. Leochico and E. John, “Evaluating Cloud Auto-Scaler Resource Allocation Planning Under High-Performance Computing Workloads”, 19th International Conference on Ubiquitous Computing and Communications (IUCC-2020), UK, December 2020.
S. Verma, Q. Wu, B. Hanindhito, G. Jha, E. John, R. Radhakrishnan and L. K. John, “Demystifying the MLPerf Training Benchmark Suite”, In the Proc. of the 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’20), Boston, MA, August 2020.
T. Banerjee, E. Adib, A. Taha and E. John, “Sequential methods for detecting a change in the distribution of an episodic process,” In the Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Virtual Barcelona, Spain, May 2020.
T. K. Kodali, Y. Zhang, E. John and W. Lin, “An Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction”, Journal of Information Science and Engineering, pp 1-12, Jan 2020.
S. Mostafa and E. John, “Resource Shared Galois Field Computation for Energy Efficient AES/CRC in IoT Applications”, IEEE Transactions on Sustainable Computing, pp. 340-348, vol. 4, Dec. 2019.
A. Owahid, and E. John “Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction”, 31st International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2019, October 15-18, 2019 – Campo Grande, MS, Brazil.
S. Mostafa, E. John and M. Panday, “Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers”, IEEE Transactions on VLSI Systems, Vol. 27. No. 4, pp. 983- 987, April, 2019.
C. Davis, A. Muthineni, and E. John, “Low-Power Advanced Encryption Standard for Implantable Cardiac Devices”, 62nd IEEE International Midwest Symposium on Circuits and Systems, Dallas, TX, Aug. 4-7, 2019.
L. John, S. Verma, Q. Wu, B. Hanindhito, R. Radhakrishnan, G, Jha and E. John, ” Demystifying Hardware Infrastructure Choices for Deep Learning using MLPref”, NVIDIA GPU Technology Conference (GTC-2019), San Jose, CA, March 2019.
S. Verma, Q. Wu, B. Hanindhito, G. Jha, E. John, R. Radhakrishnan, and L. K. John,”Metrics for Machine Learning Workload Benchmarking”, International Workshop on Performance Analysis of Machine Learning Systems (FastPath) in conjunction with ISPASS 2019. March 2019.
J. Whitehouse, Q. Wu, S. Song, E. John, A. Gerstlauer, and L. K. John, “A Study of Core Utilization and Residency in Heterogeneous Smartphone Architectures”, ACM International Conference on Performance Engineering (ICPE). April 2019.
A. Owahid, and E. John, “Wasted Dynamic Power and Correlation to Instruction Set Architecture for CPU Throttling” The Journal of Supercomputing, pp. 2436-2454, Volume 75, Number 5, May 2019.
E. Tolliver and E. John, “Power Reduction in CNNs by Modifying Floating Point Number Format for Machine Learning” 4th Annual Samsung Austin Research Center Technology Forum, Austin, TX, Oct 16, 2018.
G. Jha and E. John, “Performance Analysis of Single-Precision Floating-Point MAC for Deep Learning”, 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada, August 5th-8th, 2018.
T. A. Newton and E. John, “A Metric for Measuring Power Efficiency and Data Throughput in Mobile ad hoc Networks”, International Journal of Parallel, Emergent and Distributed Systems, pp. 556-571, March, 2018.
J. Portillo and E. John, “Using Static Hardware Wrappers to Thwart Hardware Trojans and Code Bugs at Runtime” 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada, August 5th-8th, 2018.
J. Portillo and E. John, “Detecting Vulnerabilities within Black Boxed CPUs using Assertion Based Verification for Enhanced Security”, The 2018 International Conference on Security and Management (SAM’18), Las Vegas, July 30 – August 2, 2018.
S. Koppa and E. John, “Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices”, Journal of Low Power Electronics, 14, 18 – 27., March, 2018.
D. Vernor, S. Koppa, and E. John, “Static Noise Margin Optimized 11nm Shorted-Gate and Independent-Gate Low Power 6T FINFET SRAM Topologies”, International Journal of VLSI Design & Communication Systems (VLSICS), 9(5)., October, 2018.
H. Yan, L. Jiang, L. Duan, W. Lin and E. John, “FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance”, ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 5s, October 2017.
A. Owahid and E. John, “Identifying Micro-ops for CPU Throttling to Reduce Wasted Dynamic Power” 3rd Annual Samsung Austin Research Center Technology Forum, Austin, TX, Oct 17, 2017.
P. Mariano and E. John, “Reducing Branch Penalty by an Early Branch Resolution Technique” 4th Annual Samsung Austin Research Center Technology Forum, Austin, TX, Oct 16, 2017.
P. Sarva, S. Koppa, and E. John, “An Ultra-Low Power modified SERF Adder in Sub-threshold region for Bio-medical Applications”, The 3rd International Conference on Biomedical Engineering and Sciences, BIOENG’17: Las Vegas, July 17-20, 2017.
A. Owahid and E. John, “RTL Level Instruction Profiling for CPU Throttling to Reduce Wasted Dynamic Power”, The 2017 International Symposium on Parallel And Distributed Computing And Computational Science, Las Vegas, NV, 2017.
J. Portillo and E. John, “Enhancing Trojan Detection by Finding LTL and Taint Properties in RTL Circuit Designs: A Case Study“, The 2017 International Symposium on Cyber Warfare, Cyber Defense, and Cyber Security, Las Vegas, NV, 14 – 16, Dec 2017.
J. Portillo, E. John and S. Narasimhan, “Building Trust in 3PIP using Asset-based Security Property Verification” IEEE VLSI Test Symposium 2016, Las Vegas, NV, April 25-27, 2016.
S. Koppa, M. Mohandesi and E. John “An Ultra-Low Power CR-SAR A/D Converter for Biomedical Applications”, Journal of Low Power Electronics, Vol.12, No. 4., pp. 385–393 (2016)
S. Mostafa and E. John, “Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices”, Journal of Low Power Electronics, Volume 12, Number 1, March 2016, pp. 21-29(9)
S. Koppa, P. Syam, S. Nanduru and E. John “A Quantitative Performance Analysis of FinFET Based Multiplier Circuits” 59th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, UAE, 2016
A. Ozer and E. John, “Improving the Accuracy of Bluetooth Low Energy Indoor Positioning Using Kalman Filtering”, The 2016 International Symposium on Internet of Things and Internet of Everything, , Las Vegas, Dec 15 – 17, 2016
S. Koppa, and E. John “Leakage Current Compensation in Switched Capacitor Circuits for Implantable Cardiac Devices”, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG’16), Las Vegas, NV, July 25 – 28, 2016.
S. Mostafa and E. John “Performance and Energy Evaluation of ARM Cortex Variants for Smart Cardiac Pacemaker Application”, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG’16), Las Vegas, NV, July 25 – 28, 2016.
S. Erathne, P.S. Nair and E. John, “A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors”, Journal of Low Power Electronics, Volume 11, Number 2, June 2015, pp. 103-111(9)
Vasquez, C., Krishnan, R., and John, E. (2015). Time Series Forecasting of Cloud Data Center Workloads for Dynamic Resource Provisioning. Journal of Wireless Mobile Networks, Ubiquitous Computing and Dependable Applications, 6(3).
Valliyappan, V., John, E., Krishnan, R., & Nanduru, S. (2015). Design And Implementation of Low-Power Nanoscale Cryptosystem for Group-Centric Secure Information Sharing. Research Briefs on Information & Communication Technology Evolution (Journal), 1(20).
Ninglekhu, J., Krishnan, R., John, E., & Panday, M. (2015). Securing Implantable Cardioverter Defibrillators Using Smartphones. Journal of Internet Services and Information Security, 5(2).
M. Cheboli, P.S. Nair and E. John, Speed, Power and Area Performance of ALU Implementation in the Nanoscale Domain, International Journal of Engineering, Sciences and Management (IJESM), Vol 1, Issue 1, pp. 1 – 9, Jan, 2015.
S. Mostafa and E. John “Evaluation of Embedded ISAs for Smart Cardiac Pacemaker Workloads”, in the Proceedings of the 2015 International Conference on Biomedical Engineering and Sciences (BIOENG’15), Las Vegas, NV, July 27-30, 2015.
C. Hurt and E. John, “Analysis of Memory Sensitive SPEC CPU2006 Integer Benchmarks for Big Data Benchmarking” 1st Workshop on Performance Analysis of Big Data Systems (PABS – 2015), Austin, TX, Feb, 2015.
N. Ferdous. B. Lee and E. John, “Performance Enhancement in Shared-Memory Multiprocessors Using Dynamically Classified Sharing Information” 33rd IEEE – International Performance Computing and Communications Conference IPCCC 2014, Austin, TX, Dec 5 – 7, 2014.
N. Ferdous. B. Lee and E. John “Exploiting Reuse-Frequency with Speculative and Dynamic Updates in an Enhanced Directory Based Coherence Protocol”, in The 2014 International Conference on Parallel and Distributed Processing Techniques and Applications PDPTA’14, pp. 334-350, Las Vegas, July 2014.
C. Vazquez, R. Krishnan and E. John, “Cloud Computing Benchmarking: A Survey” in the Proceedings of The 2014 International Conference on Grid & Cloud Computing & Applications GCA’14, pp. 15 – 20, Las Vegas, July 2014
Y. Zhang, M. Hays, W. Lin, and E. John, “Autonomous Control of Issue Queue Utilization for Simultaneous Multi-Threading Processors, The 22nd High Performance Computing Symposium (HPC 2014), April 13-16, 2014, Tampa, FL.
J. Whitehouse and E. John, “Leakage and Delay Analysis in FinFET Array Multipliers”, in 57th IEEE International Midwest Symposium on Circuits and Systems (MWCAS), Aug 3 – 6, 2014.
K. Leochico and E. John, “Data Retention Voltage Analysis of Various Low-Power SRAM topologies”, in 57th IEEE International Midwest Symposium on Circuits and Systems (MWCAS), Aug 3 – 6, 2014.
F. Hurtado and E. John, “A Comparative Analysis of Leakage Reduction Techniques in Nanoscale CMOS Arithmetic Circuits”, in ASEE/GSW Annual Conference, New Orleans, April 2 – 4, 2014.
H. Rios, J. Guo, B. Liu and E. John, “LEON2 Timing Performance in Automotive, Office Automation and Security Applications”, in ASEE/GSW Annual Conference, New Orleans, April 2 – 4, 2014.
M. Talsania and E. John, “A Comparative Analysis of Parallel Prefix Adders”, Proceedings of the 2013 International Conference on Computer Design, pp. 29 – 36, Las Vegas, July 2013.
R. Krishnan and E. John, “Design of a Curriculum on Cloud Computing” Proceedings of the 2013 International Conference on Frontiers in Education: Computer Science & Computer Engineering”, pp 312 – 315, Las Vegas, 2013.
P. Mishra , E. John, and W. Lin, “Static Noise Margin and Power Dissipation Analysis of various SRAM Topologies ”, IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) 2013Columbus Ohio, August 2013.
P. S. Nair, S. Erathne and E. John, “Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance”, Journal of Low Power Electronics. Volume 8, Number 1, pp. 1-8, April 2012.
M. Debnath, W. Lin and E. John, “Adaptive Instruction Dispatching Techniques for Simultaneous Multi-Threading (SMT) Processors”, Journal of Computers and Electrical Engineering, Aug. 2012
D. Subedi and E. John, “Stand-by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits using Self Adjustable Voltage level Circuit”, International Journal of VLSI Design & Communication Systems, Vol. 3, No. 5, pp 1-12, October 2012.
P. S. Nair, D. Kudithipudi, E. John and F. W. Hudson “Execution Characteristics of Embedded Applications on Pentium-4 Based Personal Computer”, Journal of Embedded Computing, pp 107 – 116, 2012
S. Eratne, E. John, and B. Lee, “Reducing Thermal Hotspots in Microprocessors with Expanded Component Sizing”, IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) 2012, Boise, Idaho, 635-638 pp.
J. Fisher, C. Romo, E. John, and W. Lin, “Design and Low Power Implementation of a Reorder Buffer”, The 2012 International Conference on Computer Design (CDES’12), pp 22 – 28, Las Vegas, NV, 2012.
R. Arun and E. John, “Performance Bound Energy Efficient L2 Cache Organization for Emerging Workload for Multi-Core Processor: A Comparison of Private and Shared Cache”, The 2012 International Conference on Computer Design (CDES’12), pp 103 – 108, Las Vegas, NV, 2012.
J. Luo, K. Morales, B. K. Lee, E. John and Y. K. Choi, “Performance-Sensitivity and Performance-Similarity Based Workload Reduction,” 31st IEEE International Performance Computing and Communications Conference (IEEE IPCCC), December 2012
A. Camacho, E. John and R. Krishnan, “Design and Low Power VLSI Implementation of Triple-DES Algorithm”, in the Proceedings The 2012 International Conference on Security and Management (SAM’12), Las Vegas, NV, July 16-19, 2012
R. Krishnan, E. John and M. Panday, Towards Security Policy and Architecture for Managing Implantable Medical Devices, in the Proceedings of the The 2012 International Conference on Security and Management (SAM’12) 2012 Las Vegas NV, July 16-19, 2012.
T. Nagaraju, C. Douglas, W. Lin and E. John, “Effective Dispatching for Simultaneous Multi-Threading (SMT) Processors by Capping Per-Thread Resource Utilization”, The Computing Science and Technology International Journal, Vol. 1, No. 2, December 2011.
S. Eratne, C. Romo, E. John, and W. Lin, “Reducing Thermal Hotspots in Multi-Core Processors Using Dynamic Core Scheduling”, The 2011 International Conference on Computer Design. (CDES’11), pp 125 – 130, Las Vegas, NV, 2011.
N. Davanam, H. Y. Kim, B. K. Lee and E. John, “Sensitivity Analysis on Hardware Resources in SMT Processors,” The 2011 International Conference on Computer Design (CDES’11), 2011
C. Romo, S. Eratne, E. John, and B. K. Lee, “Leakage – Delay Tradeoff in Wide-Bit Nanoscale CMOS Adders”, The 2011 International Conference on Computer Design. (CDES’11), 146 – 149, Las Vegas, NV, 2011.
Binu. P. John, A. Agrawal, B. Steigerwald and E. John, “Impact of Operating System Behavior on Battery Life”. Journal of Low Power Electronics. Volume 6, Number 1, pp. 10-17, April 2010.
P. S. Nair, Eratne, and E. John, “A Quasi-Power-Gated Low-Leakage Stable SRAM Cell”, 53rd IEEE Midwest Symposium on Circuits and Systems, Seattle, WA, 2010
S. Eratne, P. Nair, and E. John, “Leakage Control in Full Adders with Selectively Stacked Inverters”, 53rd IEEE Midwest Symposium on Circuits and Systems, Seattle, WA, 2010
S. Eratne, C. Romo, E. John, and Byeong K Lee, “Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors”, The 2010 International Conference on Computer Design (CDES’10), July 2010, Las Vegas, NV, 2010
S. Eratne, C. Romo, and E. John, “Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase”, The 2010 International Conference on Computer Design (CDES’10), July 2010, Las Vegas, NV, 2010
S. Eratne, C. Romo, and E. John, “Use of Increased Transistor Gate Length for Leakage Reduction in Caches”, 53rd IEEE Mid-West Symposium on Circuits and Systems, Seattle, WA, 2010
Byeong Kil Lee, S. Raghunath and E. John, “Architectural Sensitivity Analysis on Network Workloads,” The 2010 International Conference on Computer Design (CDES’10), July 2010, Las Vegas, NV, 2010.
C. Martinez, M. Pinnamaneni and E. John “Performance of Commercial Multimedia Workloads on the Intel Pentium 4: A Case Study”, International Journal of Computers and Electrical Engineering, Vol. 35, No.1, pp 18 – 32, January 2009.
D. Kudithipudi and E. John “Implications of Gated-Vss Technique on Leakage Power in Embedded Caches”, International Journal of Embedded Systems, Vol 4, No.1, pp 17 – 26, 2009.
B. P. John, P.S. Nair, E. John and F. Hudson, “Performance Measurement of Single, Dual and Quad Core Machines using SPEC CPU 2006”, Proceedings of the International Conference on Computer Design, CDES ’09, Las Vegas, pp. 143-149, July 2009.
P. S. Nair, S. Koppa, E. John and D. Kudithipudi “Topology Selection of FPGA Look-up Tables for Low-Leakage Operation” The 19th European Conference on Circuit Theory and Design (ECCTD 09), pp 73-76, Turkey, August 2009.
C. Isen, L. John and E. John, “A Tale of Two Processors: Revisiting the RISC-CISC Debate “. 2009 SPEC Benchmark Workshop, Springer, Lecture Notes in Computer Science LNCS 5419, pp. 57-76, January 2009.
P. S. Nair, S. Koppa, E. John, “ A Comparative Analysis of Coarse-grain and Fine grain Power Gating for FPGA Lookup Tables”, 52nd IEEE International Midwest Symposium on Circuits and Systems (IEEE-MWSCAS’09), pp. 507 – 510, August 2009.
D. Kudithipudi, S. Petko and E. John “Cache Design for Multimedia Workloads: Power and Energy Tradeoffs”, IEEE Transactions on Multimedia, Vol. 10, No. 6, pp. 1013 – 1021 October, 2008.
C. B. Smith, D. R. Mandel and E. John, “A Superscalar Simulation Employing Poisson Distributed Stalls”, International Journal of Computers and Electrical Engineering, pp. 192 – 201,Vol. 34, No. 3, May 2008.
D. Kudithipudi, and E. John, “On Estimation of Static Power-Performance in TCAM” 51st IEEE Midwest Symposium on Circuits and Systems, pp.783-786 MWSCAS’08, August 10 – 13, 2008.
A. Hussein, H. Saleh, B. Mohammad, and E. John, “Optimum Organization of SRAM-based Memory for Leakage Power Reduction” 51st IEEE Midwest Symposium on Circuits and Systems, pp.775-778 MWSCAS’08, August 10 – 13, 2008.
P. S. Nair, S. Eratne, and E. John, “Topology-related effects of Gated-Vdd and Gated Vss techniques on full-adder Leakage and Delay at 65nm and 45 nm”, in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS ’08), 2008, pp. 972-975.
S. Eratne, S. Puthenpurayil, E. John, “Energy Efficient Lossless Image Compression,” in 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 2008, pp. 344-347
P. S. Nair, S. K. K. Venkataswamy, S. Eratne and E. John, “Impact of High-K Dielectric Transistors on Full-Adder Delay and Leakage Characteristics”, in Proc. IASTED Int. Conf. Circuits and Systems (CS ’08), 2008, pp. 55-60.
S. Eratne, S. Puthenpurayil, E. John, “Energy Efficiency of Data Compression with Wavelets”, 2008 International Conference on Image Processing, Computer Vision, and Pattern Recognition WORLDCOMP’08, Las Vegas, NV, 2008
P. S. Nair, S. Eratne, E. John, “Effects of Register File Organization on Leakage Power Consumption,” 2008 International Conference on Computer Design WORLDCOMP’08, Las Vegas, NV, 2008
P. S. Nair and E. John, “Analyzing the Performance of Personal Computers based on Intel microprocessors for Sequence Aligning Bioinformatics Applications” International Journal of Bioinformatics Research and Applications, Vol. 3, No.2, pp. 187-205, 2007
D. Kudithipudi and E. John, “Static Power Analysis and Estimation in TCAM cells”, Journal of Low Power Electronics, Vol. 3, pp. 293 – 301, 2007
S. Eratne, P. Nair and E. John, “Leakage current control of nanoscale full adder cells using input vectors”, IEEE International Conference on Design & Technology of Integrated Systems, pp. 185 – 189, DTIS’07, Rabat, Morocco, September 2007.
D. Kudithipudi, P. Nair and E. John, “On Estimation and Optimization of Leakage Power in CMOS Multipliers” IEEE Midwest Symposium on Circuits and Systems, MWSCAS’07, August 2007.
P. S. Nair and E. John, “Performance Analysis of an Intel Pentium-4-based Personal Computer for Multiple Sequence Alignment” International Conference on Computer Design, CDES’07, Las Vegas, NV, June 2007.
B. K. Lee, L. K. John and E. John, “Architectural Enhancements for Network Congestion Control Applications” IEEE Transactions on VLSI Systems, Vol. 14, No. 6, pp. 609-615, June, 2006
R. Valliyappan, E. John, R. Kuzet, and H. Foltz “Low Power RF CMOS Receiver Front-end Using Reflex Amplifier” The International Signal Processing Conference, Santa Clara, California, October 30-November 2, 2006.
N. Marupudi, E. John and F. Hudson, “Fingerprint Verification Based on Image Filtering of Ridges” The International Signal Processing Conference, Santa Clara, California, October 30-November 2, 2006.
J. Tang, F. Hudson and E. John, “Remote Fingerprint Entry Verification Using Bluetooth Wireless Technology” The International Signal Processing Conference, Santa Clara, California, October 30-November 2, 2006.
P. S. Nair, D. Kudithipudi, E. John and F. Hudson, “Performance Analysis of Embedded Applications on a Pentium-4 Based Machine” ESA’06 – The 2006 International Conference on Embedded Systems & Applications, Las Vegas, Nevada, June 26-29, 2006
P. S. Nair and E. John, “Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study” BIOCOMP’06- The 2006 International Conference on Bioinformatics & Computational Biology, Las Vegas, Nevada, June 26-29, 2006
Ryan Sweet, Pradeep Nair and E.John, “Impact of Input Vectors on Leakage Current in nanoscale Complimentary MOS Gates”, UTSA Engineering, Science and Biotechnology Student Conference, San Antonio, November 2006
C. Martinez, M. Pinnamaneni and E. John, “Multimedia Workloads versus SPEC CPU2000”, 2006 SPEC Benchmark Workshop, Austin, TX, January 23, 2006
P. S. Nair, D. Kudithipudi and E. John, “Design and Implementation of a CMOS Non-Restoring Divider”, IEEE Region 5 Conference, San Antonio, TX, April 6- 8, 2006
N. Marupudi, E. John and F. Hudson “Fingerprint Verification in Multimodal Biometrics”, IEEE Region 5 Conference, San Antonio, TX, April 6- 8, 2006.
S. Eratne, D. Kudithipudi and E. John, “Performance Analysis of Full Adders in Nanoscale CMOS Design”, IEEE Region 5 Conference, San Antonio, TX, April 6- 8, 2006
D. Kudithipudi and E. John “Implementation of Low Power Digital Multipliers using 10 Transistor Adder Blocks”, Journal of Low Power Electronics, Vol. 1, pp. 286 – 296, 2005
R. Kuzet, M. Chilikuri, H. Foltz and E. John, “RF CMOS Self-Oscillating Gilbert Cell Mixer”, Proceedings of IASTED International Conference on Circuits, Signals, and Systems (CSS 2005), October 24 – 26, 2005, in Marina Del Rey, USA
D. Kudithipudi and E. John, “Parametrical Characterization of Leakage Power in Embedded System Caches using Gated-Vss”, Proceedings of International Association of Science and Technology for Development on Circuits, Signals and Systems, Marina Del Rey, October 2005
D. Kudithipudi and E. John, “A Combinatorial Approach to Suppress Leakage in Nanoscale SRAM Cells”, in the proceedings of IEEE Midwest Symposium on Circuits and Systems-2005, Cincinnati, Ohio, August 2005.
B. K. Lee, L. K. John and E. John, “Architectural Support for Accelerating Congestion Control Applications in Network Processors” IEEE 16th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2005). Greece, July 2005.
D. Kudithipudi and E.John, “A Framework to Moderate Leakage Power in Nanoscale CMOS SoC Devices”, Poster Presentation, NanoSummit Research Conference, Houston, July 2005.
D. Kudithipudi and E. John, “Parametrical Characterization of leakage power in Nanoscale Technologies”, Poster Presentation, IBM’s Austin Conference on Energy Efficient Design, March 2005.
D. Kudithipudi, S. Petko and E. John, “Cache leakage power Analysis in Embedded Application” in proceedings of IEEE Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Vol. II, pp. 517-520, 2004.
D. Kudithipudi, R. Kota, E. John and Z. P. Tanner, “Impact of Nanotechnology on the Performance of CMOS Digital Multilpliers”, in the Proceedings of International Conference on Circuits, Signals and Systems, IASTED 2004, Clearwater Beach, FL, November 2004.
D. Kudithipudi, R. Kota, E. John and Z. P. Tanner, “Power, Area and Delay Performance Comparison of Multipliers for Embedded Systems” in the Proceedings of International Signal Processing Conference, San Jose, California, Oct, 2004
R. Kuzet, M. Chilikuri, S. Puthenpurayil, H. Foltz and E. John, “RF CMOS receiver Front-End Using Reflex Amplifier” Proceedings of IASTED International Conference on Communication Systems and Applications (CSA), Banff, AB, Canada – July 8-10, 2004
S. Petko, D. Kudithipudi and E. John, “Memory System Characterization for Multimedia Applications” International Signal Processing Conference (ISPC), Dallas, TX. March 31 – April 3, 2003
M. Wasiewicz, D. Kudithipudi and E. John “Low Power Parallel Digital Multipliers using 10 Transistor Adder Circuits” International Signal Processing Conference (ISPC), Dallas, TX. March 31 – April 3, 2003
A. K. Ojha, and E. John, “A Paradigm for Testing RISC Processor –Based Complex System–on-Chip (SOC),” Proc. of the IEEE Southeastcon 2003, Ocho Rios, Jamaica, March 2003.
E. John, S. Petko, L. John and J. Law, “Access Time and Energy Tradeoffs for Caches in High Frequency Microprocessors” in Proceedings of 45th IEEE International Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August, 2002.
S. Petko, D. Kudithipudi and E. John, “Cache performance of Video Computation Workloads” Proceedings of the International Workshop on Digital and Computational Video, Clearwater, FL, November 2002.
A. Moreno and E. John, “A Flexible Design for Timing Signals Generation for the Conversion of Computer Video Formats to SDTV 480P”, IEEE Transactions on Consumer Electronics pp.1081-1086, Vol. 45, November 1999.
R. Shalem, E. John and L. John, “A Novel Low Power Energy Recovery Full Adder Cell” Proceedings of the Great Lake Symposium on VLSI, pp. 380-383, 1999
M. Rodriguez and E. John, “Design and VLSI Implementation of Arithmetic Circuits”, Proceedings of the ASEE/GSW Conference, 1999.
L. K. John and E. John, “A Dynamically Reconfigurable Interconnect for Array Processors”, IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 150-157, March 1998.
E. John, F. Hudson and L. Kurian “Hybrid Tree: A Scalable Optoelectronic Interconnection Network for Parallel Computing” Proceedings of the 31st Hawaii International Conference on System Sciences, Vol. VII, pp. 466-474, January 1998.
H. Saenz and E. John, “Design and FPGA Implementation of an 8-bit Processor”,pp.228- 233, Proceedings of the ASEE/GSW Conference, 1998.
L. Roitberg and E. John ” Voice Recognition Hardware Interface Using Field Programmable Gate Arrays” pp.230-233, Proceedings of the ASEE/GSW Conference, 1997.
E. Lott and E. John ” Design and Simulation of Solid state Semiconductor Devices” pp.222-225, Proceedings of the ASEE/GSW Conference, 1997.
D. Ault, B. Lozano and E. John “3-D Graphics Computation using Field Programmable Gate Arrays” pp.226-229, Proceedings of the ASEE/GSW Conference, 1997.
P. T. Hulina, L. D. Coraor, L. Kurian, and E. John, “Design and VLSI Implementation of an Address Generation Coprocessor”, IEE Proceedings on Computers and Digital Techniques, Vol 142, No. 2, pp. 145- 151, March 1995.
M. B. Das, J. W. Chen, and E. John, “Design of Optoelectronic Integrated Circuit Receivers for High Sensitivity and Maximally Flat Frequency Response”, IEEE/OSA Journal of Lightwave Technology, Vol. 13, No.9, pp. 1876-1884, 1995.
L. Kurian, D. Brewer, E. John, “Design of a Highly Reconfigurable Interconnect for Array Processors”, Proceedings of the 8th International Conference on VLSI Design, pp. 321-325, January 1995.
E. John, M. B. Das, W-Y. Yang, T.S. Miller, and D. Miller “ Fabrication and Performance of a Novel Ultra-Low Capacitance MSM Photodetector for High Speed OEIC Receiver Applications” Proceedings of the 7th International Conference on InP and Related Materials, May 9-13, 1995, Sapporo, Japan.
E. John and M. B. Das, “Design and Performance Analysis of InP-Based High-Speed and High Sensitivity Optoelectronic Integrated Receivers”, IEEE Transactions on Electron Devices, Vol. 42, No. 2, pp. 162-172, 1994.
E. John and M. B. Das, “A New Design Approach for a High Transimpedance and Low-Noise Optoelectronic Integrated Lightwave Receiver with 24GHz Bandwidth” Microwave and Optical Technology Letters, Vol. 7, No.6, pp. 259-262, April 1994.
E. John and M.B. Das, “Circuit Optimization of Optoelectronic Integrated Lightwave Receivers for Maximum Bandwidth and High-Sensitivity”, Proceedings of the Conference on Emerging Optoelectronic Technologies, 18-22, July 1994.
E. John, M. B. Das, Y. W. Yang, and S. M. J. Liu “Extraction of High Frequency Equivalent Network Parameters of HBT’s by Low Frequency Extrapolation of Microwave S-Parameter Data” Proceedings of the 14th IEEE/ Cornel Conference on High-Speed Semiconductor Devices and Circuits, pp 141-147, 1993.
P. T. Hulina, L. Kurian, E. John and L. D. Coraor, “Design and VLSI Implementation of an Access Processor for a Decoupled Architecture”, Journal of Microprocessors and Microsystems, Vol. 16, No. 5, pp. 237-247, May 1992.
E. John and M. B. Das, “Speed and Sensitivity Limitations of Optoelectronic Receivers Based on MSM Photodiode and Millimeter Wave HBTs on InP Substrate”, IEEE Photonics Technology Letters, vol. 4, No. 10, pp 1145-1148, 1992.
